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PSoC(R) 3: CY8C32 Family Data Sheet
Programmable System-on-Chip (PSoC(R))
General Description
With its unique array of configurable blocks, PSoC(R) 3 is a true ystem level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C). In addition to communication interfaces, the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC CreatorTM, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
Single cycle 8051 CPU core DC to 50 MHz operation Multiply and divide instructions Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple security features Up to 8-KB flash error correcting code (ECC) or configuration storage Up to 8 KB SRAM Up to 2 KB electrically erasable programmable read-only memory (EEPROM), 1 M cycles, and 20 years retention 24-channel direct memory access (DMA) with multilayer AHB[1] bus access * Programmable chained descriptors and priorities * High bandwidth 32-bit transfer support Low voltage, ultra low-power Wide operating voltage range: 0.5 V to 5.5 V High efficiency boost regulator from 0.5-V through 1.8-V to 5.0-V output 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz Low-power modes including: * 1-A sleep mode with real-time clock (RTC) and low-voltage detect (LVD) interrupt * 200-nA hibernate mode with RAM retention Versatile I/O system 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two USBIOs[2]) Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments[2] CapSense(R) support from any GPIO[3] 1.2-V to 5.5-V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt-trigger transistor-transistor logic (TTL) inputs All GPIO configurable as open drain high/low, pull-up/pull-down, High Z, or strong output Configurable GPIO pin state at power-on reset (POR) 25 mA sink on SIO Digital peripherals 16 to 24 programmable PLD based universal digital blocks (UDB) Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2] Up to four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals * 8-, 16-, 24-, and 32-bit timers, counters, and PWMs * Serial peripheral interface (SPI), universal asynchronous transmitter receiver (UART), and I2C * Many others available in catalog Library of advanced peripherals * Cyclic redundancy check (CRC) * Pseudo random sequence (PRS) generator * Local interconnect network (LIN) bus 2.0 * Quadrature decoder Analog peripherals (1.71 V VDDA 5.5 V) 1.024 V 0.9-percent internal voltage reference across -40C to +85C (14 ppm/C) Configurable delta-sigma ADC with 8- to12-bit resolution * Programmable gain stage: x0.25 to x16 * 12-bit mode, 192-ksps, 66-dB signal to noise and distortion ratio (SINAD), 1-bit INL/DNL One 8-bit, 8-Msps IDAC or 1-Msps VDAC Two comparators with 95 ns response time CapSense support Programming, debug, and trace JTAG (4-wire), serial wire debug (SWD) (2-wire), and single wire viewer (SWV) interfaces Eight address and one data breakpoint 4-KB instruction trace buffer Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces Precision, programmable clocking 3- to 24-MHz internal oscillator over full temperature and voltage range 4- to 25-MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 50 MHz 32.768-kHz watch crystal oscillator Low-power internal oscillator at 1, 33, and 100 kHz Temperature and packaging -40C to +85C degrees industrial temperature 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options
Notes 1. AHB - AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 106 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation Document Number: 001-56955 Rev. *J
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 30, 2011
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PSoC(R) 3: CY8C32 Family Data Sheet
Contents
1. Architectural Overview ..................................................... 3 2. Pinouts ............................................................................... 5 3. Pin Descriptions .............................................................. 10 4. CPU ................................................................................... 11 4.1 8051 CPU ................................................................. 11 4.2 Addressing Modes .................................................... 11 4.3 Instruction Set .......................................................... 12 4.4 DMA and PHUB ....................................................... 16 4.5 Interrupt Controller ................................................... 18 5. Memory ............................................................................. 22 5.1 Static RAM ............................................................... 22 5.2 Flash Program Memory ............................................ 22 5.3 Flash Security ........................................................... 22 5.4 EEPROM .................................................................. 22 5.5 Nonvolatile Latches (NVLs) ...................................... 23 5.6 External Memory Interface ....................................... 24 5.7 Memory Map ............................................................ 24 6. System Integration .......................................................... 26 6.1 Clocking System ....................................................... 26 6.2 Power System .......................................................... 29 6.3 Reset ........................................................................ 33 6.4 I/O System and Routing ........................................... 34 7. Digital Subsystem ........................................................... 40 7.1 Example Peripherals ................................................ 41 7.2 Universal Digital Block .............................................. 44 7.3 UDB Array Description ............................................. 47 7.4 DSI Routing Interface Description ............................ 47 7.5 USB .......................................................................... 49 7.6 Timers, Counters, and PWMs .................................. 49 7.7 I2C ............................................................................ 49 8. Analog Subsystem .......................................................... 51 8.1 Analog Routing ......................................................... 52 8.2 Delta-sigma ADC ...................................................... 54 8.3 Comparators ............................................................. 55 8.4 LCD Direct Drive ...................................................... 57 8.5 CapSense ................................................................. 57 8.6 Temp Sensor ............................................................ 57 8.7 DAC .......................................................................... 58 9. Programming, Debug Interfaces, Resources ................ 59 9.1 JTAG Interface ......................................................... 59 9.2 Serial Wire Debug Interface ..................................... 59 9.3 Debug Features ........................................................ 59 9.4 Trace Features ......................................................... 59 9.5 Single Wire Viewer Interface .................................... 60 9.6 Programming Features ............................................. 60 9.7 Device Security ........................................................ 60 10. Development Support ................................................... 61 10.1 Documentation ....................................................... 61 10.2 Online ..................................................................... 61 10.3 Tools ....................................................................... 61 11. Electrical Specifications ............................................... 62 11.1 Absolute Maximum Ratings .................................... 62 11.2 Device Level Specifications .................................... 63 11.3 Power Regulators ................................................... 67 11.1 Inputs and Outputs ................................................. 71 11.2 Analog Peripherals ................................................. 79 11.3 Digital Peripherals .................................................. 91 11.4 Memory .................................................................. 94 11.5 PSoC System Resources ..................................... 100 11.6 Clocking ................................................................ 102 12. Ordering Information ................................................... 106 12.1 Part Numbering Conventions ............................... 108 13. Packaging ..................................................................... 109 14. Acronyms ..................................................................... 112 15. Reference Documents ................................................. 113 16. Document Conventions .............................................. 114 16.1 Units of Measure .................................................. 114 17. Revision History .......................................................... 115 18. Sales, Solutions, and Legal Information ................... 119
Document Number: 001-56955 Rev. *J
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PSoC(R) 3: CY8C32 Family Data Sheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC(R)) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram
Analog Interconnect Digital Interconnect
SIO GPIOs
Usage Example for UDB
Sequencer
4- 33 MHz ( Optional )
System Wide Resources
Xtal Osc
Digital System
Universal Digital Block Array ( 24 x UDB)
8- Bit Timer UDB Quadrature Decoder UDB 16- Bit PWM UDB 16- Bit PRS UDB UDB UDB
I2C
Master / Slave
22
UDB UDB 8- Bit Timer Logic UDB UDB UDB
UDB I2C Slave UDB
UDB 8- Bit SPI
12- Bit SPI UDB UDB
GPIOs
UDB
UDB
IMO
4x Timer Counter PWM
FS USB 2.0
USB PHY
Clock Tree
Logic UDB UART UDB UDB 12- Bit PWM UDB UDB UDB
GPIOs
32. 68 KHz 7 ( Optional )
RTC Timer
System Bus
WDT and Wake GPIOs
Memory System
EEPROM SRAM
CPU System
8051 or Cortex M3 CPU Interrupt Controller
Program & Debug
Program Debug & Trace
GPIOs
EMIF ILO Clocking System
FLASH
PHUB DMA
Boundary Scan
GPIOs
SIOs
Power Management System
Analog System
LCD Direct Drive
POR and LVD Sleep Power 1.71 to 5.5V 1.8V LDO SMP Temperature Sensor CapSense
ADC
Del Sig ADC DAC 2x CMP
+ GPIOs -
0. 5 to 5.5V ( Optional )
Figure 1-1 illustrates the major components of the CY8C32 family. They are: 8051 CPU subsystem Nonvolatile subsystem Programming, debug, and test subsystem Inputs and outputs Clocking Power Digital subsystem Analog subsystem Document Number: 001-56955 Rev. *J
PSoC's digital subsystem provides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the Digital System Interconnect (DSI). It also provides functional flexibility through an array of small, fast, low-power UDBs. PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit using boolean primitives by means of graphical design entry. Each UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals.
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In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C32 family these blocks can include four 16-bit timers, counters, and PWM blocks; I2C slave, master, and multimaster; and FS USB. For more details on the peripherals see the "Example Peripherals" section on page 41 of this datasheet. For information on UDBs, DSI, and other digital blocks, see the "Digital Subsystem" section on page 40 of this datasheet. PSoC's analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.9-percent error over temperature and voltage. The configurable analog subsystem includes: Analog muxes Comparators Voltage references ADC DAC All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. The heart of the analog subsystem is a fast, accurate, configurable delta-sigma ADC with these features: Less than 100 V offset A gain error of 0.2 percent INL less than 1 LSB DNL less than 1 LSB SINAD better than 66 dB This converter addresses a wide variety of precision analog applications, including some of the most demanding sensors. A high-speed voltage or current DAC supports 8-bit output signals at an update rate of 8 Msps in current DAC (IDAC) and 1 Msps in voltage DAC (VDAC). It can be routed out of any GPIO pin. You can create higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADC and DAC, the analog subsystem provides multiple comparators. See the "Analog Subsystem" section on page 51 of this datasheet for more details. PSoC's 8051 CPU subsystem is built around a single cycle pipelined 8051 8-bit processor running at up to 50 MHz. The CPU subsystem includes a programmable nested vector interrupt controller, DMA controller, and RAM. PSoC's nested vector interrupt controller provides low latency by allowing the CPU to vector directly to the first address of the interrupt service routine, bypassing the jump instruction required by other architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. The processor speed itself is configurable, allowing you to tune active power consumption for specific applications. PSoC's nonvolatile subsystem consists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 64 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling bootloaders. You can enable an ECC for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Up to 2 KB of byte-writeable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after POR. The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the VDDIO pins. Every GPIO has analog I/O, LCD drive[4], CapSense[5], flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow Voh to be set independently of VDDIO when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with FS USB the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. All of the features of the PSoC I/Os are covered in detail in the "I/O System and Routing" section on page 34 of this datasheet. The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The Internal Main Oscillator (IMO) is the master clock base for the system, and has 1-percent accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 24 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. The device provides a PLL to generate system clock frequencies up to 50 MHz from the IMO, external crystal, or external reference clock. It also contains a separate, very low-power Internal Low-Speed Oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in RTC applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. The CY8C32 family supports a wide supply operating range from 1.71 V to 5.5 V. This allows operation from regulated supplies such as 1.8 5 percent, 2.5 V 10 percent, 3.3 V 10 percent, or 5.0 V 10 percent, or directly from a wide range of battery types. In addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5 V.
Notes 4. This feature on select devices only. See Ordering Information on page 106 for details. 5. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-56955 Rev. *J
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PSoC(R) 3: CY8C32 Family Data Sheet
This enables the device to be powered directly from a single battery or solar cell. In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3-V supply for LCD glass drive. The boost's output is available on the VBOOST pin, allowing other devices in the application to be powered from the PSoC. PSoC supports a wide range of low-power modes. These include a 200-nA hibernate mode with RAM retention and a 1-A sleep mode with RTC. In the second mode the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 1.2 mA when the CPU is running at 6 MHz, or 0.8 mA running at 3 MHz. The details of the PSoC power modes are covered in the "Power System" section on page 29 of this datasheet. PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for programming, debug, and test. The 1-wire SWV may also be used for "printf" style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins. Using these standard interfaces enables you to debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. PSoC supports on-chip break points and 4-KB instruction and data race memory for debug. Details of the programming, test, and debugging interfaces are discussed in the "Programming, Debug Interfaces, Resources" section on page 59 of this datasheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-1 through Figure 2-4. Using the Vddio pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each Vddio may sink up to 100 mA total to its associated I/O pins. On the 68 pin and 100 pin devices each set of Vddio associated pins may sink up to 100 mA. The 48-pin device may sink up to 100 mA total for all Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all Vddio1 plus Vddio3 associated I/O pins.
Figure 2-1. 48-pin SSOP Part Pinout
(SIO ) P12[2] (SIO ) P12[3] (GPIO) P0[0] (GPIO) P0[1] (GPIO) P0[2] (Extref0, GPIO) P0[3] Vddio0 (GPIO) P0[4] (GPIO) P0[5] (IDAC0, GPIO) P0[6] (GPIO) P0[7] Vccd Vssd Vddd (GPIO) P2[3] (GPIO) P2[4] Vddio2 (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] Vssb Ind Vboost Vbat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) Vddio3 P15[1] (GPIO, MHz XTAL: Xi) P15[0] (GPIO, MHz XTAL: Xo) Vccd Vssd Vddd [6] P15[7] (USBIO, D-, SW DCK) [6] P15[6] (USBIO, D+, SW DIO) P1[7] (GPIO) P1[6] (GPIO) Vddio1 P1[5] (GPIO, nTRST) P1[4] (GPIO, TDI) P1[3] (GPIO, TDO, SW V) P1[2] (GPIO, configurable XRES) P1[1] (GPIO, TCK, SW DCK) P1[0] (GPIO, TMS, SW DIO)
Lines show Vddio to I/O supply association
SSOP
Note 6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *J
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Figure 2-2. 48-pin QFN Part Pinout[8]
P2[5] (GPIO) Vddio2 P2[4] (GPIO) P2[3] (GPIO) Vddd Vssd Vccd P0[7] (GPIO) P0[6] (GPIO, IDAC0) P0[5] (GPIO) P0[4] (GPIO) Vddio0 (GPIO) P2[6] (GPIO) P2[7] Vssb Ind Vboost Vbat (GPIO, TMS, SWDIO) P1[0] (GPIO, TCK, SWDCK) P1[1] (GPIO, Configurable XRES) P1[2] (GPIO, TDO, SWV) P1[3] (GPIO, TDI) P1[4] (GPIO, nTRST) P1[5] 48 47 46 45 44 43 42 41 40 39 38 37 Lines show Vddio to I/O supply association 1 2 3 4 5 6 7 8 9 10 11 12
QFN
( Top View )
Notes 7. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. 8. PPins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *J
Vddio1 (GPIO) P1[6] (GPIO) P1[7] [7] (USBIO, D+, SWDIO) P15[6] [7] (USBIO, D-, SWDCK) P15[7] Vddd Vssd Vccd (GPIO, MHz XTAL: Xo) P15[0] (GPIO, MHz XTAL: Xi) P15[1] Vddio3 (SIO, I2C1: SCL) P12[0]
13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
P0[3] (Extref0, GPIO) P0[2] (GPIO) P0[1] (GPIO) P0[0] (GPIO) P12[3] (SIO) P12[2] (SIO) Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA)
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Figure 2-3. 68-pin QFN Part Pinout[10]
P0[7] (GPIO) P0[6] (GPIO, IDAC0)
P15[5] (GPOI) P15[4] (GPIO) Vddd Vssd Vccd
P2[5] (GPIO)
Vddio2 P2[4] (GPIO) P2[3] (GPIO)
P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO)
68 67
66 65
64
63 62 61 60 59
58 57 56
55 54
(GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Ind Vboost Vbat Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1
53 52
P0[5] (GPIO) P0[4] (GPIO) Vddio0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 Lines show Vddio to I/O supply association 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 31 32 33 34
QFN
(Top View)
P0[3] (GPIO, Extref0) P0[2] (GPIO) P0[1] (GPIO) P0[0] (GPIO) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, 12C1: SCL) P3[7] (GPIO) P3[6] (GPIO) Vddio3
18 19
20 21 22
23
24 25 26 27 Vddd Vssd Vccd (MHz XTAL: Xo, GPIO) P15[0]
(GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (USBIO, D+, SWDIO) P15[6] (USBIO, D-, SWDCK) P15[7]
(GPIO) P1[6]
(MHz XTAL: Xi, GPIO) P15[1] (GPIO) P3[0] (GPIO) P3[1] (Extref1, GPIO) P3[2]
28 29 30
(GPIO) P3[3] (GPIO) P3[4]
Notes 9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. 10. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
Document Number: 001-56955 Rev. *J
(GPIO) P3[5]
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Figure 2-4. 100-pin TQFP Part Pinout
P0[6] (GPIO, IDAC0) P0[5] (GPIO) P0[4] (GPIO) 77 76 (GPIO) P3[5] Vddio3 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Vddio0 P0[3] (GPIO,Extref0) P0[2] (GPIO) P0[1] (GPIO) P0[0] (GPIO) P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca NC NC NC NC NC NC P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) P3[7] (GPIO) P3[6] (GPIO)
P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPIO)
P15[4] (GPIO) P6[3] (GPIO) P6[2] (GPIO) P6[1] (GPIO) P6[0] (GPIO)
P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO)
Vccd P4[7] (GPIO) P4[6] (GPIO)
100 99
98 97
96
95 94 93 92 91
90 89 88
87 86
85 84 83 82 81 80 42 43 44 45 46
26 27
28 29 30
31
32 33 34 35
36 37 38
39 40 41
(GPIO) P5[5] (GPIO) P5[6] (GPIO) P5[7] [11] (USBIO, D+, SWDIO) P15[6]
Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a two layer board. The two pins labeled Vddd must be connected together. The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on page 29. The trace between the two Vccd pins should be as short as possible. The two pins labeled Vssd must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC(R) 3 and PSoC 5.
Note 11. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *J
[11] (USBIO, D-, SWDCK) P15[7] Vddd Vssd Vccd NC NC (MHz XTAL: Xo, GPIO) P15[0] (MHz XTAL: Xi, GPIO) P15[1] (GPIO) P3[0] (GPIO) P3[1] (Extref1, GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4]
(GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (GPIO) P5[4]
Vddio1
47 48
(GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] Vssb Ind Vboost Vbat Vssd XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Lines show Vddio to I/O supply association
TQFP
79 78
P4[5] (GPIO) P4[4] (GPIO) P4[3] (GPIO) P4[2] (GPIO) P0[7] (GPIO)
Vddio2
Vddd Vssd
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Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections
Vddd Vddd
Vddd
C1 1 uF
C2 0.1 uF Vccd
C6 0.1 uF Vssd
Vddd 100 99 98 97 96 95 94 93 92 91 90 89 Vddd 88 Vssd 87 86 85 84 83 82 81 80 79 78 77 76 Vssd Vssd
U2 CY8C55xx
Vddio2 P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] Vddd Vssd Vccd P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] OA2-, P0[5] OA2+, P0[4]
Vdda Vddd 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C8 0.1 uF Vssd Vssd Vssd Vdda Vssa Vcca C9 1 uF Vssa Vdda C17 1 uF
Vssd
Vssd
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 P32 47 48 49 50
Vddd
Vddio1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] USB D+, P15[6] USB D-, P15[7] Vddd Vssd Vccd NC NC P15[0], MHzXout P15[1], MHzXin P3[0], IDAC1 P3[1], IDAC3 P3[2], OA3-, REF1 P3[3], OA3+ P3[4], OA1P3[5], OA1+ Vddio3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] Vssb Ind Vboost Vbat Vssd XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWIO, TMS P1[1], SWDIO, TCK P1[2] P1[3], SWV, TDO P1[4], TDI P1[5], nTRST
Vddio0 OA0-, REF0, P0[3] OA0+, P0[2] OA0out, P0[1] OA2out, P0[0] P4[1] P4[0] SIO, P12[3] SIO, P12[2] Vssd Vdda Vssa Vcca NC NC NC NC NC NC kHzXin, P15[3] kHzXout, P15[2] SIO, P12[1] SIO, P12[0] OA3out, P3[7] OA1out, P3[6]
C10 0.1 uF
Vssa
Vddd C11 0.1 uF C14 0.1 uF Vssd
Vssd
Vddd
Vccd
C12 0.1 uF Vssd C16 0.1 uF
C13 10 uF, 6.3 V Vssa
C15 1 uF
Vssa
Vssd
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6 on page 10.
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Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Vssa Vddd Vssd Vdda
Vssd Plane
Vssa Plane
3. Pin Descriptions
IDAC0 Low resistance output pin for high current DAC (IDAC). Extref0, Extref1 External reference input to the analog system. GPIO General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense. I2C0: SCL, I2C1: SCL I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA I C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. Ind Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi 32.768-kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi 4- to 25- MHz crystal oscillator pin.
2
nTRST Optional JTAG test reset programming and debug port connection to reset the JTAG connection. SIO Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK Serial wire debug clock programming and debug port connection. SWDIO Serial wire debug input and output programming and debug port connection. SWV. Single wire viewer debug output. TCK JTAG test clock programming and debug port connection. TDI JTAG test data in programming and debug port connection. TDO JTAG test data out programming and debug port connection. TMS JTAG test mode select programming and debug port connection.
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USBIO, D+ Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are Do Not Use (DNU) on devices without USB. USBIO, D- Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are No Connect (NC) on devices without USB. Vboost Power sense connection to boost pump. Vbat Battery supply to boost pump. Vcca Output of analog core regulator and input to analog core. Requires a 1-F capacitor to VSSA. Regulator output not for external use. Vccd Output of digital core regulator and input to digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1-F capacitor to VSSD; see Power System on page 29. Regulator output not for external use. Vdda Supply for all analog peripherals and analog core regulator. Vdda must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. Vddd Supply for all digital peripherals and digital core regulator. VDDA must be less than or equal to VDDA. Vssa Ground for all analog peripherals. Vssb Ground connection for boost pump. Vssd Ground for all digital logic and I/O pins. Vddio0, Vddio1, Vddio2, Vddio3 Supply for I/O pins. See pinouts for specific I/O pin to Vddio mapping. Each Vddio must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to Vdda. If the I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used then that Vddio should be tied to ground (Vssd or Vssa). XRES (and configurable XRES) External reset pin. Active low with internal pull-up. Pin P1[2] may be configured to be a XRES pin; see "Nonvolatile Latches (NVLs)" on page 23.
4. CPU
4.1 8051 CPU
The CY8C32 devices use a single cycle 8051 CPU, which is fully compatible with the original MCS-51 instruction set. The CY8C32 family uses a pipelined RISC architecture, which executes most instructions in 1 to 2 cycles to provide peak performance of up to 24 MIPS with an average of 2 cycles per instruction. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. The 8051 CPU subsystem includes these features: Single cycle 8051 CPU Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up to 8 KB of SRAM Programmable nested vector interrupt controller Direct memory access (DMA) controller Peripheral HUB (PHUB) External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051: Direct Addressing: The operand is specified by a direct 8-bit address field. Only the internal RAM and the SFRs can be accessed using this mode. Indirect Addressing: The instruction specifies the register which contains the address of the operand. The registers R0 or R1 are used to specify the 8-bit address, while the data pointer (DPTR) register is used to specify the 16-bit address. Register Addressing: Certain instructions access one of the registers (R0 to R7) in the specified register bank. These instructions are more efficient because there is no need for an address field. Register Specific Instructions: Some instructions are specific to certain registers. For example, some instructions always act on the accumulator. In this case, there is no need to specify the operand. Immediate Constants: Some instructions carry the value of the constants directly instead of an address. Indexed Addressing: This type of addressing can be used only for a read of the program memory. This mode uses the data pointer as the base and the accumulator value as an offset to read a program memory. Bit Addressing: In this mode, the operand is one of 256 bits.
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4.3 Instruction Set
The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include: Arithmetic instructions Logical instructions Data transfer instructions Boolean instructions Program branching instructions
4.3.1 Instruction Set Summary 4.3.1.1 Arithmetic Instructions Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes are used for addition, subtraction, multiplication, division, increment, and decrement operations. Table 4-1 Table 4-1 on page 12lists the different arithmetic instructions.
Table 4-1. Arithmetic Instructions Mnemonic ADD ADD ADD ADD A,Rn A,Direct A,@Ri A,#data Description Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry Add direct byte to accumulator with carry Add indirect RAM to accumulator with carry Add immediate data to accumulator with carry Subtract register from accumulator with borrow Subtract direct byte from accumulator with borrow Subtract indirect RAM from accumulator with borrow Subtract immediate data from accumulator with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply accumulator and B Divide accumulator by B Decimal adjust accumulator Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 2 3 3 1 2 3 3 1 2 6 3
ADDC A,Rn ADDC A,Direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,Direct SUBB A,@Ri SUBB A,#data INC INC INC INC DEC DEC DEC DEC INC MUL DIV DAA A Rn Direct @Ri A Rn Direct @Ri DPTR
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4.3.1.2 Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2Table 4-2 on page 13 shows the list of logical instructions and their description. Table 4-2. Logical Instructions Mnemonic ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR A,Rn A,Direct A,@Ri A,#data Direct, A Direct, #data A,Rn A,Direct A,@Ri A,#data Direct, A Direct, #data A,Rn A,Direct A,@Ri A,#data Direct, A Direct, #data A A A A A Description AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte XOR register to accumulator XOR direct byte to accumulator XOR indirect RAM to accumulator XOR immediate data to accumulator XOR accumulator to direct byte XOR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right though carry Swap nibbles within accumulator Bytes 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Cycles 1 2 2 2 3 3 1 2 2 2 3 3 1 2 2 2 3 3 1 1 1 1 1 1 1
RRC A SWAP A
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4.3.1.3 Data Transfer Instructions The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer includes transfer between any two core RAM locations or SFRs. These instructions can use direct, indirect, register, and immediate addressing. The xdata RAM transfer includes only the transfer between the accumulator and the xdata RAM location. It can use only indirect addressing. The lookup tables involve nothing but the read of program memory using the Indexed Table 4-3. Data Transfer Instructions Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A,Rn A,Direct A,@Ri A,#data Rn,A Rn,Direct Rn, #data Direct, A Direct, Rn Direct, Direct Direct, @Ri Direct, #data @Ri, A @Ri, Direct @Ri, #data DPTR, #data16
addressing mode. Table 4-3 lists the various data transfer instructions available. 4.3.1.4 Boolean Instructions The 8051 core has a separate bit-addressable memory location. It has 128 bits of bit addressable RAM and a set of SFRs that are bit addressable. The instruction set includes the whole menu of bit operations such as move, set, clear, toggle, OR, and AND instructions and the conditional jump instructions. Table 4-4 on page 15Table 4-4 lists the available Boolean instructions.
Description Move register to accumulator Move direct byte to accumulator Move indirect RAM to accumulator Move immediate data to accumulator Move accumulator to register Move direct byte to register Move immediate data to register Move accumulator to direct byte Move register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load data pointer with 16-bit constant Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move external RAM (8-bit) to accumulator Move external RAM (16-bit) to accumulator Move accumulator to external RAM (8-bit) Move accumulator to external RAM (16-bit) Push direct byte onto stack Pop direct byte from stack Exchange register with accumulator Exchange direct byte with accumulator Exchange indirect RAM with accumulator Exchange low order indirect digit RAM with accumulator
Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
Cycles 1 2 2 2 1 3 2 2 2 3 3 3 2 3 2 3 5 4 4 3 5 4 3 2 2 3 3 3
MOVC A, @A+DPTR MOVC A, @A + PC MOVX A,@Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH Direct POP XCH XCH XCH Direct A, Rn A, Direct A, @Ri
XCHD A, @Ri
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Table 4-4. Boolean Instructions Mnemonic CLR CLR C bit Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND complement of direct bit to carry OR direct bit to carry OR complement of direct bit to carry Move direct bit to carry Move carry to direct bit Jump if carry is set Jump if no carry is set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Description Bytes 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 Cycles 1 3 1 3 1 3 2 2 2 2 2 3 3 3 5 5 5
SETB C SETB bit CPL CPL ANL ANL C bit C, bit C, /bit
ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC JB rel bit, rel JNC rel JNB bit, rel JBC bit, rel
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4.3.1.5 Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5 shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A + DPTR JZ rel JNZ rel CJNE A,Direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn,rel DJNZ Direct, rel NOP Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if accumulator is zero Jump if accumulator is nonzero Compare direct byte to accumulator and jump if not equal Compare immediate data to accumulator and jump if not equal Compare immediate data to register and jump if not equal Compare immediate data to indirect RAM and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation Bytes 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 Cycles 4 4 4 4 3 4 3 5 4 4 5 4 4 5 4 5 1
4.4 DMA and PHUB
The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of: A central hub that includes the DMA controller, arbiter, and router Multiple spokes that radiate outward from the hub to most peripherals There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests. 4.4.1 PHUB Features CPU and DMA controller are both bus masters to the PHUB Eight Multi-layer AHB Bus parallel access paths (spokes) for peripheral access
Simultaneous CPU and DMA access to peripherals located on different spokes Simultaneous DMA source and destination burst transactions on different spokes Supports 8, 16, 24, and 32-bit addressing and data Table 4-6. PHUB Spokes and Peripherals PHUB Spokes Peripherals 0 SRAM 1 IOs, PICU, EMIF 2 PHUB local configuration, Power manager, Clocks, IC, SWV, EEPROM, Flash programming interface 3 Analog interface and trim, Decimator 4 USB, USB, I2C, Timers, Counters, and PWMs 5 Reserved 6 UDBs group 1 7 UDBs group 2
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4.4.2 DMA Features 24 DMA channels Each channel has one or more transaction descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined TDs can be dynamically updated Eight levels of priority per channel Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction Each channel can generate up to two interrupts per transfer Transactions can be stalled or canceled Supports transaction size of infinite or 1 to 64k bytes TDs may be nested and/or chained for complex transactions 4.4.3 Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100 percent of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in Table 4-7 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. Table 4-7. Priority Levels Priority Level 0 1 2 3 4 5 6 7 % Bus Bandwidth 100.0 100.0 50.0 25.0 12.5 6.2 3.1 1.5
When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made. 4.4.4 Transaction Modes Supported The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to: 4.4.4.1 Simple DMA In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic timing diagrams of DMA read and write cycles are shown in Figure 4-1. For more description on other transfer modes, refer to the Technical Reference Manual.
Figure 4-1. DMA Timing Diagram
ADDRESS Phase CLK DATA Phase CLK ADDRESS Phase DATA Phase
ADDR 16/32
A
B
ADDR 16/32
A
B
WRITE
WRITE
DATA
DATA (A)
DATA
DATA (A)
READY Basic DMA Read Transfer without wait states
READY Basic DMA Write Transfer without wait states
4.4.4.2 Auto Repeat DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. 4.4.4.3 Ping Pong DMA A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete. 4.4.4.4 Circular DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD.
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4.4.4.5 Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain. 4.4.4.6 Packet Queuing DMA Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase "subchains" can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. 4.4.4.7 Nested DMA One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD's configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the second TD's configuration. This process repeats as often as necessary.
4.5 Interrupt Controller
The interrupt controller provides a mechanism for hardware resources to change program execution to a new address, independent of the current task being executed by the main code. The interrupt controller provides enhanced features not found on original 8051 interrupt controllers: Thirty two interrupt vectors Jumps directly to ISR anywhere in code space with dynamic vector addresses Multiple sources for each vector Flexible interrupt to vector matching Each interrupt vector is independently enabled or disabled Each interrupt can be dynamically assigned one of eight priorities Eight level nestable interrupts Multiple I/O interrupt vectors Software can send interrupts Software can clear pending interrupts When an interrupt is pending, the current instruction is completed and the program counter is pushed onto the stack. Code execution then jumps to the program address provided by the vector. After the ISR is completed, a RETI instruction is executed and returns execution to the instruction following the previously interrupted instruction. To do this the RETI instruction pops the program counter from the stack. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. Fixed function interrupts and all interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Figure 4-2 on page 19 represents typical flow of events when an interrupt triggered. Figure 4-3 on page 20 shows the interrupt structure and priority polling.
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Figure 4-2. Interrupt Processing Timing Diagram
1 2 3 4 5 6 7 8 9 10 11
S
CLK Arrival of new Interrupt INT_INPUT Pend bit is set on next system clock active edge PEND Interrupt is posted to ascertain the priority POST Interrupt request sent to core for processing IRQ cleared after receiving IRA POST and PEND bits cleared after IRQ is sleared
S S S S S
0x0000
IRQ ACTIVE_INT_NUM (#10)
NA
0x0010
The active interrupt number is posted to core
INT_VECT_ADDR
NA
The active interrupt ISR address is posted to core
S S
NA
S S S
Completing current instruction and branching to vector address Complete ISR and return
TIME
IRA
IRC Interrupt generation and posting to CPU CPU Response Int. State Clear
Notes 1: Interrupt triggered asynchronous to the clock 2: The PEND bit is set on next active clock edge to indicate the interrupt arrival 3: POST bit is set following the PEND bit 4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks) 5: ISR address is posted to CPU core for branching 6: CPU acknowledges the interrupt request 7: ISR address is read by CPU for branching 8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core 10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles) 11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status The total interrupt latency (ISR execution) = POST + PEND + IRQ + IRA + Completing current instruction and branching = 1+1+1+2+7 cycles = 12 cycles
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Figure 4-3. Interrupt Structure
Interrupts form Fixed function blocks, DMA and UDBs
Interrupts 0 to 30 from UDBs
Interrupt Polling logic Interrupt Enable/ Disable, PEND and POST logic
0
Highest Priority
Interrupts 0 to 30 from Fixed Function Blocks
1
IRQ
0 to 30
Individual Enable Disable bits Interrupt 2 to 29
ACTIVE_INT_NUM
Polling sequence
Interrupts 0 to 30 from DMA
Interrupt routing logic to select 31 sources
8 Level Priority decoder for all interrupts
[15:0]
INT_VECT_ADDR
IRA
IRC
30
Global Enable disable bit
Lowest Priority
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Table 4-8. Interrupt Vector Table # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Fixed Function LVD ECC Reserved Sleep (Pwr Mgr) PICU[0] PICU[1] PICU[2] PICU[3] PICU[4] PICU[5] PICU[6] PICU[12] PICU[15] Comparators Combined Reserved I2C Reserved Timer/Counter0 Timer/Counter1 Timer/Counter2 Timer/Counter3 USB SOF Int USB Arb Int USB Bus Int USB Endpoint[0] Reserved LCD Reserved Decimator Int PHUB Error Int EEPROM Fault Int DMA phub_termout0[0] phub_termout0[1] phub_termout0[2] phub_termout0[3] phub_termout0[4] phub_termout0[5] phub_termout0[6] phub_termout0[7] phub_termout0[8] phub_termout0[9] UDB udb_intr[0] udb_intr[1] udb_intr[2] udb_intr[3] udb_intr[4] udb_intr[5] udb_intr[6] udb_intr[7] udb_intr[8] udb_intr[9]
phub_termout0[10] udb_intr[10] phub_termout0[11] udb_intr[11] phub_termout0[12] udb_intr[12] phub_termout0[13] udb_intr[13] phub_termout0[14] udb_intr[14] phub_termout0[15] udb_intr[15] phub_termout1[0] phub_termout1[1] phub_termout1[2] phub_termout1[3] phub_termout1[4] phub_termout1[5] phub_termout1[6] phub_termout1[7] phub_termout1[8] udb_intr[16] udb_intr[17] udb_intr[18] udb_intr[19] udb_intr[20] udb_intr[21] udb_intr[22] udb_intr[23] udb_intr[24] udb_intr[25]
USB Endpoint Data phub_termout1[9]
phub_termout1[10] udb_intr[26] phub_termout1[11] udb_intr[27] phub_termout1[12] udb_intr[28] phub_termout1[13] udb_intr[29] phub_termout1[14] udb_intr[30] phub_termout1[15] udb_intr[31]
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5. Memory
5.1 Static RAM
CY8C32 Static RAM (SRAM) is used for temporary data storage. Up to 8 KB of SRAM is provided and can be accessed by the 8051 or the DMA controller. See Memory Map on page 24. Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4-KB blocks are accessed.
security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the "Device Security" section on page 60). For more information about how to take full advantage of the security features in PSoC, see the PSoC 3 TRM. Table 5-1. Flash Protection Protection Setting Unprotected Factory Upgrade Allowed External read and write - + internal read and write External write + internal read and write External read External read and write External read and write + internal write Not Allowed
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ECC data. The main flash memory area contains up to 64 KB of user program space. Up to an additional 8 KB of flash space is available for Error Correcting Codes (ECC). If ECC is not used this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. Flash is read in units of rows; each row is 9 bytes wide with 8 bytes of data and 1 byte of ECC data. When a row is read, the data bytes are copied into an 8-byte instruction buffer. The CPU fetches its instructions from this buffer, for improved CPU performance. Flash programming is performed through a special interface and preempts code execution out of flash. The flash programming interface performs flash erasing, programming and setting code protection levels. Flash in-system serial programming (ISSP), typically used for production programming, is possible through both the SWD and JTAG interfaces. In-system programming, typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any communications protocol.
Field Upgrade Internal read and write Full Protection Internal read Disclaimer
Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products.
5.3 Flash Security
All PSoC devices include a flexible flash-protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ECC or configuration data. A total of up to 256 blocks is provided on 64-KB flash devices. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile memory. The CY8C32 has up to 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is divided into 128 rows of 16 bytes each. The CPU can not execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled in firmware.
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5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table 5-2. Table 5-2. Device Configuration NVL Register Map Register Address 0x00 0x01 0x02 0x03 7 6 5 4 3 2 1 0 PRT3RDM[1:0] PRT12RDM[1:0] XRESMEN DIG_PHS_DLY[3:0] ECCEN DPS[1:0] PRT2RDM[1:0] PRT6RDM[1:0] PRT1RDM[1:0] PRT5RDM[1:0] PRT0RDM[1:0] PRT4RDM[1:0] PRT15RDM[1:0]
The details for individual fields and their factory default settings are shown in Table 5-3:. Table 5-3. Fields and Factory Default Settings Field PRTxRDM[1:0] Description Settings Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog See "Reset Configuration" on page 40. All pins of the port 01b - high impedance digital are set to the same mode. 10b - resistive pull up 11b - resistive pull down 0 (default for 68-pin and 100-pin parts) - GPIO Controls whether pin P1[2] is used as a GPIO or as an external reset. See "Pin Descriptions" on page 10, XRES 1 (default for 48-pin parts) - external reset description. Controls the usage of various P1 pins as a debug port. See "Programming, Debug Interfaces, Resources" on page 59. 00b - 5-wire JTAG 01b (default) - 4-wire JTAG 10b - SWD 11b - debug ports disabled
XRESMEN
DPS{1:0]
ECCEN
Controls whether ECC flash is used for ECC or for general 0 (default) - ECC disabled configuration and data storage. See "Flash Program 1 - ECC enabled Memory" on page 22. Selects the digital clock phase delay. See the TRM for details.
DIG_PHS_DLY[3:0]
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited - see "Nonvolatile Latches (NVL))" on page 95.
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5.6 External Memory Interface
CY8C32 provides an external memory interface (EMIF) for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. At 33 MHz, each memory access cycle takes four bus clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C32 supports only one type of external memory device at a time. External memory can be accessed via the 8051 xdata space; up to 24 address bits can be used. See "xdata Space" section on page 26. The memory can be 8 or 16 bits wide.
Figure 5-1. EMIF Block Diagram
Address Signals
External MEM_ ADDR[23:0] _ IO PORTs
Data, Address, and Control Signals
IO IF
Data Signals
External MEM_ DATA[15:0] _ IO PORTs
Control Signals
PHUB
Data, Address, and Control Signals
IO PORTs
Control
DSI Dynamic Output Control
UDB
DSI to Port
Data, Address, and Control Signals
EM Control Signals
Other Control Signals
EMIF
5.7 Memory Map
The CY8C32 8051 memory map is very similar to the MCS-51 memory map. 5.7.1 Code Space The CY8C32 8051 code space is 64 KB. Only main flash exists in this space. See the "Flash Program Memory" section on page 22.
5.7.2 Internal Data Space The CY8C32 8051 internal data space is 384 bytes, compressed within a 256-byte space. This space consists of 256 bytes of RAM (in addition to the SRAM mentioned in Static RAM on page 22) and a 128-byte space for Special Function Registers (SFRs). See Figure 5-2. The lowest 32 bytes are used for 4 banks of registers R0-R7. The next 16 bytes are bit-addressable.
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Figure 5-2. 8051 Internal Data Space
0x00 0x1F 0x20 0x2F 0x30 0x7F 0x80 Upper Core RAM Shared with Stack Space (indirect addressing) SFR Special Function Registers (direct addressing) 4 Banks, R0-R7 Each Bit-Addressable Area Lower Core RAM Shared with Stack Space (direct and indirect addressing)
In addition to the register or bit address modes used with the lower 48 bytes, the lower 128 bytes can be accessed with direct or indirect addressing. With direct addressing mode, the upper 128 bytes map to the SFRs. With indirect addressing mode, the upper 128 bytes map to RAM. Stack operations use indirect addressing; the 8051 stack space is 256 bytes. See the "Addressing Modes" section on page 11
0xFF
5.7.3 SFRs The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-4. Table 5-4. SFR Map Address 0xF8 0xF0 0xE8 0xE0 0xD8 0xD0 0xC8 0xC0 0xB8 0xB0 0xA8 0xA0 0x98 0x90 0x88 0x80 B SFRPRT12DR ACC SFRPRT6DR PSW SFRPRT5DR SFRPRT4DR - SFRPRT3DR IE P2AX SFRPRT2DR SFRPRT1DR - SFRPRT0DR 0/8 SFRPRT15DR - SFRPRT12PS - SFRPRT6PS - SFRPRT5PS SFRPRT4PS - SFRPRT3PS - - SFRPRT2PS SFRPRT1PS SFRPRT0PS SP 1/9 SFRPRT15PS 2/A SFRPRT15SEL SFRPRT12SEL MXAX - SFRPRT6SEL - SFRPRT5SEL SFRPRT4SEL - SFRPRT3SEL - SFRPRT1SEL SFRPRT2SEL - SFRPRT0SEL DPL0 - - - - - - - - - - - - - DPX0 - DPH0 - DPL1 3/B - - - - - - - - - - - - - 4/C - - - - - - - - - - - - - DPX1 - DPH1 5/D - - - - - - - - - - - - - - - DPS 6/E - - - - - - - - - - - - - - - - 7/F
The CY8C32 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C32 devices add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C32 family. XData Space Access SFRs The 8051 core features dual DPTR registers for faster data transfer operations. The data pointer select SFR, DPS, selects which data pointer register, DPTR0 or DPTR1, is used for the following instructions: MOVX @DPTR, A MOVX A, @DPTR MOVC A, @A+DPTR
JMP @A+DPTR INC DPTR MOV DPTR, #data16 The extended data pointer SFRs, DPX0, DPX1, MXAX, and P2AX, hold the most significant parts of memory addresses during access to the xdata space. These SFRs are used only with the MOVX instructions. During a MOVX instruction using the DPTR0/DPTR1 register, the most significant byte of the address is always equal to the contents of DPX0/DPX1. During a MOVX instruction using the R0 or R1 register, the most significant byte of the address is always equal to the contents of MXAX, and the next most significant byte is always equal to the contents of P2AX.
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I/O Port SFRs The I/O ports provide digital input sensing, output drive, pin interrupts, connectivity for analog inputs and outputs, LCD, and access to peripherals through the DSI. Full information on I/O ports is found in I/O System and Routing on page 34. I/O ports are linked to the CPU through the PHUB and are also available in the SFRs. Using the SFRs allows faster access to a limited set of I/O port registers, while using the PHUB allows boot configuration and access to all I/O port registers. Each SFR supported I/O port provides three SFRs: SFRPRTxDR sets the output data state of the port (where x is port number and includes ports 0 - 6, 12 and 15). The SFRPRTxSEL selects whether the PHUB PRTxDR register or the SFRPRTxDR controls each pin's output buffer within the port. If a SFRPRTxSEL[y] bit is high, the corresponding SFRPRTxDR[y] bit sets the output state for that pin. If a SFRPRTxSEL[y] bit is low, the corresponding PRTxDR[y] bit sets the output state of the pin (where y varies from 0 to 7). The SFRPRTxPS is a read only register that contains pin state values of the port pins. 5.7.3.1 xdata Space The 8051 xdata space is 24-bit, or 16 MB in size. The majority of this space is not "external"--it is used by on-chip components. See Table 5-5. External, that is, off-chip, memory can be accessed using the EMIF. See External Memory Interface on page 24. Table 5-5. XDATA Data Address Map Address Range 0x00 0000 - 0x00 1FFF 0x00 4000 - 0x00 42FF 0x00 4300 - 0x00 43FF 0x00 4400 - 0x00 44FF 0x00 4500 - 0x00 45FF 0x00 4700 - 0x00 47FF 0x00 4900 - 0x00 49FF SRAM Clocking, PLLs, and oscillators Power management Interrupt controller Ports interrupt control Flash programming interface I2C controller Purpose
Table 5-5. XDATA Data Address Map (continued) Address Range 0x05 0220 - 0x05 02F0 0x08 0000 - 0x08 1FFF Purpose Debug controller Flash ECC bytes 0x01 0000 - 0x01 FFFF Digital Interconnect configuration
0x80 0000 - 0xFF FFFF External Memory Interface
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate up to a 50 MHz clock, accurate to 1 percent over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything the user wants, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system's requirements. It greatly speeds the design process. PSoC Creator allows you to build clocking systems with minimal input. You can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent PSoC. Key features of the clocking system include: Seven general purpose clock sources 3- to 24-MHz IMO, 1 percent at 3 MHz 4- to 25-MHz external crystal oscillator (MHzECO) Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 29 DSI signal from an external I/O pin or other logic 24- to 50- MHz fractional PLL sourced from IMO, MHzECO, or DSI Clock Doubler 1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and sleep timer 32.768-kHz external crystal oscillator (kHzECO) for RTC IMO has a USB mode that auto locks to the USB bus clock requiring no external crystal for USB. (USB equipped parts only) Independently sourced clock in all clock dividers Eight 16-bit clock dividers for the digital system Four 16-bit clock dividers for the analog system Dedicated 16-bit divider for the bus clock Dedicated 4-bit divider for the CPU clock Automatic clock configuration in PSoC Creator
0x00 4E00 - 0x00 4EFF Decimator 0x00 4F00 - 0x00 4FFF Fixed timer/counter/PWMs 0x00 5000 - 0x00 51FF 0x00 5400 - 0x00 54FF 0x00 5800 - 0x00 5FFF 0x00 6000 - 0x00 60FF 0x00 6400 - 0x00 6FFF 0x00 7000 - 0x00 7FFF 0x00 8000 - 0x00 8FFF I/O ports control External Memory Interface (EMIF) control registers Analog Subsystem interface USB controller UDB configuration PHUB configuration EEPROM
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Table 6-1. Oscillator Summary Source IMO MHzECO DSI PLL Doubler ILO kHzECO Fmin 3 MHz 4 MHz 0 MHz 24 MHz 12 MHz 1 kHz 32 kHz Tolerance at Fmin 1% over voltage and temperature Crystal dependent Input dependent Input dependent Input dependent -50%, +100% Crystal dependent Fmax 24 MHz 25 MHz 50 MHz 50 MHz 48 MHz 100 kHz 32 kHz Figure 6-1. Clocking Subsystem
3-24 MHz IMO 4-25 MHz ECO External IO or DSI 0-50 MHz 32 kHz ECO 1,33,100 kHz ILO
Tolerance at Fmax 4% Crystal dependent Input dependent Input dependent Input dependent -55%, +100% Crystal dependent
Startup Time 10 s max 5 ms typ, max is crystal dependent Input dependent 250 s max 1 s max 15 ms max in lowest power mode 500 ms typ, max is crystal dependent
12-48 MHz Doubler CPU Clock Divider 4 bit 24-50 MHz PLL System Clock Mux Bus Clock Divider 16 bit
s k e w s k e w s k e w s k e w
CPU Clock
Bus Clock
Digital Clock Divider 16 bit
Digital Clock Divider 16 bit
Analog Clock Divider 16 bit
Digital Clock Divider 16 bit 7
Digital Clock Divider 16 bit 7
Analog Clock Divider 16 bit
Digital Clock Divider 16 bit
Digital Clock Divider 16 bit
Analog Clock Divider 16 bit
Digital Clock Divider 16 bit
Digital Clock Divider 16 bit
Analog Clock Divider 16 bit
6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs the IMO is the only clock source required, due to its 1-percent accuracy. The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from 1 percent at 3 MHz, up to 4-percent at 24 MHz. The IMO, in conjunction with the PLL, allows generation of CPU and system clocks up to the device's maximum frequency (see Phase-locked Loop) The IMO provides clock outputs at 3, 6, 12, and 24 MHz.
6.1.1.2 Clock Doubler The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works for input frequency ranges of 6 to 24 MHz (providing 12 to 48 MHz at the output). It can be configured to use a clock from the IMO, MHzECO, or the DSI (external pin). The doubler is typically used to clock the USB. 6.1.1.3 Phase-locked Loop The PLL allows low-frequency, high-accuracy clocks to be multiplied to higher frequencies. This is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time.
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The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 50 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate to generate the CPU and system clocks up to the device's maximum frequency. The PLL achieves phase lock within 250 s (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Disable the PLL before entering low-power modes. 6.1.1.4 Internal Low-Speed Oscillator The ILO provides clock frequencies for low-power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1 kHz clock (CLK1K) is typically used for a background `heartbeat' timer. This clock inherently lends itself to low-power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). The central timewheel is a 1 kHz, free running, 13-bit counter clocked by the ILO. The central timewheel is always enabled, except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low-power mode. Firmware can reset the central timewheel. Systems that require accurate timing should use the RTC capability instead of the central timewheel. The 100-kHz clock (CLK100K) works as a low-power system clock to run the CPU. It can also generate time intervals such as fast sleep intervals using the fast timewheel. The fast timewheel is a 100-kHz, 5-bit counter clocked by the ILO that can also be used to wake the system. The fast timewheel settings are programmable, and the counter automatically resets when the terminal count is reached. This enables flexible, periodic wakeups of the CPU at a higher rate than is allowed using the central timewheel. The fast timewheel can generate an optional interrupt each time the terminal count is reached. The 33-kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768-kHz ECO clock with no need for a crystal. 6.1.2 External Oscillators 6.1.2.1 MHz External Crystal Oscillator The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports a wide variety of crystal types, in the range of 4 to 25 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see "Phase-locked Loop" section on page 27). The GPIO pins connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz Crystal Osc
XCLK_MHZ
Xi (Pin P15[1]) External Components
Xo (Pin P15[0]) 4 - 25 MHz crystal Capacitors
6.1.2.2 32.768-kHz ECO The 32.768-kHz External Crystal Oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal (see Figure 6-3). The 32kHzECO also connects directly to the sleep timer and provides the source for the RTC. The RTC uses a 1-second interrupt to implement the RTC functionality in firmware. The oscillator works in two distinct power modes. This allows users to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram
32 kHz Crystal Osc
XCLK32K
Xi (Pin P15[3]) External Components
Xo (Pin P15[2]) 32 kHz crystal Capacitors
6.1.2.3 Digital System Interconnect The DSI provides routing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and Universal Digital Blocks. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock Page 28 of 119
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dividers. This is only possible if there are multiple precision clock sources. 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design's requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees. The system clock is used to select and supply the fastest clock in the system for general system clock requirements and clock synchronization of the PSoC device. Bus Clock 16-bit divider uses the system clock to generate the system's bus clock used for data transfers. Bus clock is the source clock for the CPU clock divider. Eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design's requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the Universal Digital Blocks (UDBs) and fixed function Timer/Counter/PWMs can also generate clocks. Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as ADC. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise.
Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50 percent duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 USB Clock Domain The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48 MHz frequency. This frequency can be generated from different sources, including DSI clock at 48 MHz or doubled value of 24 MHz from internal oscillator, DSI signal, or crystal oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also includes two internal 1.8 V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in Figure 6-4. The two Vccd pins must be shorted together, with as short a trace as possible, and connected to a 1-F 10-percent X5R capacitor. The power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator.
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Figure 6-4. PSoC Power System
Vddio2 1 F Vddd Vddio0
0.1F Vddio2 I/ O Supply Vddd Vccd Vssd
0.1F I/O Supply Vddio0
I2C Regulator
0.1F
Digital Domain
Sleep Regulator
Vdda Vdda
Vssd
Digital Regulators
Analog Regulator
Vcca 1 F Vssa
0.1F .
Analog Domain
Hibernate Regulator
Vddio1 Vccd I/O Supply Vddd Vssd I/O Supply Vddio3 Vddio3
0.1F 0.1F Vddio1 Vddd
0.1F
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6.
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6.2.1 Power Modes PSoC 3 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low-power and portable devices. PSoC 3 power modes, in order of decreasing power consumption are: Active Alternate Active Sleep Hibernate Table 6-2. Power Modes Power Modes Active Description
Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and RTC functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 illustrates the allowable transitions between power modes.
Entry Condition Wakeup Source Any interrupt
Active Clocks
Regulator
Primary mode of operation, all Wakeup, reset, peripherals available (program- manual register mable) entry Manual register Similar to Active mode, and is entry typically configured to have fewer peripherals active to reduce power. One possible configuration is to use the UDBs for processing, with the CPU turned off All subsystems automatically disabled Manual register entry
Any All regulators available. (programmable) Digital and analog regulators can be disabled if external regulation used. Any All regulators available. (programmable) Digital and analog regulators can be disabled if external regulation used.
Alternate Active
Any interrupt
Sleep
Comparator, ILO/kHzECO PICU, I2C, RTC, CTW, LVD
Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Only hibernate regulator active.
Hibernate
All subsystems automatically Manual register disabled entry Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained
PICU
Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Active Alternate Active Sleep Hibernate Wakeup Time - - <15 s Current (typ) 1.2 mA[12] - 1 A Code Execution Yes User defined No Digital Resources All All I2C Analog Resources All All Comparator Clock Sources Available All All ILO/kHzECO Wakeup Sources - - Comparator, PICU, I2C, RTC, CTW, LVD PICU Reset Sources All All XRES, LVD, WDR XRES
<100 s
200 nA
No
None
None
None
Note 12. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 63.
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Figure 6-5. Power Mode Transitions
Active
6.2.1.5 Wakeup Events Wakeup events are configurable and can come from an interrupt or device reset. A wakeup event restores the system to active mode. Firmware enabled interrupt sources include internally generated interrupts, power supervisor, central timewheel, and I/O interrupts. Internal interrupt sources can come from a variety of peripherals, such as analog comparators and UDBs. The central timewheel provides periodic interrupts to allow the system to wake up, poll peripherals, or perform real-time functions. Reset event sources include the external reset I/O pin (XRES), WDT, and Precision Reset (PRES). 6.2.2 Boost Converter Applications that use a supply voltage of less than 1.71 V, such as solar or single cell battery supplies, may use the on-chip boost converter. The boost converter may also be used in any system that requires a higher operating voltage than the supply provides. For instance, this includes driving 5.0 V LCD glass in a 3.3 V system. The boost converter accepts an input voltage as low as 0.5 V. With one low cost inductor it produces a selectable output voltage sourcing enough current to operate the PSoC and other on-board components. The boost converter accepts an input voltage from 0.5 V to 5.5 V (VBAT), and can start up with VBAT as low as 0.5 V. The converter provides a user configurable output voltage of 1.8 to 5.0 V (VBOOST). VBAT is typically less than VBOOST; if VBAT is greater than or equal to VBOOST, then VBOOST will be the same as VBAT. The block can deliver up to 50 mA (IBOOST) depending on configuration. Four pins are associated with the boost converter: VBAT, VSSB, VBOOST, and Ind. The boosted output voltage is sensed at the VBOOST pin and must be connected directly to the chip's supply inputs. An inductor is connected between the VBAT and Ind pins. You can optimize the inductor value to increase the boost converter efficiency based on input voltage, output voltage, current and switching frequency. The External Schottky diode shown in Figure 6-6 is required only in cases when VBOOST > 3.6 V. Figure 6-6. Application for Boost Converter
Manual Sleep Hibernate
Buzz Alternate Active
6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or disabled. When a resource is disabled, the digital clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. User firmware can dynamically control subsystem power by setting and clearing bits in the active configuration template. The CPU can disable itself, in which case the CPU is automatically reenabled at the next wakeup event. When a wakeup event occurs, the global mode is always returned to active, and the CPU is automatically enabled, regardless of its template settings. Active mode is the default global power mode upon boot. 6.2.1.2 Alternate Active Mode Alternate Active mode is very similar to Active mode. In alternate active mode, fewer subsystems are enabled, to reduce power consumption. One possible configuration is to turn off the CPU and flash, and run peripherals at full speed. 6.2.1.3 Sleep Mode Sleep mode reduces power consumption when a resume time of 15 s is acceptable. The wake time is used to ensure that the regulator outputs are stable enough to directly enter active mode. 6.2.1.4 Hibernate Mode In hibernate mode nearly all of the internal functions are disabled. Internal voltages are reduced to the minimal level to keep vital systems alive. Configuration state is preserved in hibernate mode and SRAM memory is retained. GPIOs configured as digital outputs maintain their previous values and external GPIO pin interrupt settings are preserved. The device can only return from hibernate mode in response to an external I/O interrupt. The resume time from hibernate mode is less than 100 s.
Vboost Optional Schottky Diode Only required Vboost >3.6 V
Vdda Vddd Vddio
Ind 22 F 0. 1 F
10 H
SMP
PSoC
22 F
Vbat Vssb Vssa Vssd
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PSoC(R) 3: CY8C32 Family Data Sheet
The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz, or 32 kHz to optimize efficiency and component cost. The 100 kHz, 400 kHz, and 2 MHz switching frequencies are generated using oscillators internal to the boost converter block. When the 32-kHz switching frequency is selected, the clock is derived from a 32 kHz external crystal oscillator. The 32-kHz external clock is primarily intended for boost standby mode. At 2 MHz the Vboost output is limited to 2 x Vbat, and at 400 kHz Vboost is limited to 4 x Vbat. The boost converter can be operated in two different modes: active and standby. Active mode is the normal mode of operation where the boost regulator actively generates a regulated output voltage. In standby mode, most boost functions are disabled, thus reducing power consumption of the boost circuit. The converter can be configured to provide low-power, low-current regulation in the standby mode. The external 32 kHz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. This is called automatic thump mode (ATM). The boost typically draws 200 A in active mode and 12 A in standby mode. The boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. Table 6-4 lists the boost power modes available in different chip power modes. Table 6-4. Chip and Boost Power Modes Compatibility Boost Power Modes Boost can be operated in either active or standby mode. Chip - Sleep mode Boost can be operated in either active or standby mode. However, it is recommended to operate boost in standby mode for low-power consumption Chip - Hibernate mode Boost can only be operated in active mode. However, it is recommended not to use boost in chip hibernate mode due to high current consumption in boost active mode If the boost converter is not used in a given application, tie the VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin unconnected. Chip Power Modes Chip - Active mode
by firmware within a certain period of time, the watchdog timer generates a reset. Software - The device can be reset under program control. Figure 6-7. Resets
Vddd Vdda
Power Voltage Level Monitors Reset Pin
Processor Interrupt
External Reset
Reset Controller
System Reset
Watchdog Timer
Software Reset Register
The term device reset indicates that the processor as well as analog and digital peripherals and registers are reset. A reset status register holds the source of the most recent reset or power voltage monitoring interrupt. The program may examine this register to detect and report exception conditions. This register is cleared after a power-on reset. 6.3.1 Reset Sources 6.3.1.1 Power Voltage Level Monitors IPOR - Initial Power-on Reset At initial power-on, IPOR monitors the power voltages VDDD and VDDA, both directly at the pins and at the outputs of the corresponding internal regulators. The trip level is not precise. It is set to approximately 1 volt, which is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 100 ns wide. It may be much wider if one or more of the voltages ramps up slowly. To save power the IPOR circuit is disabled when the internal digital supply is stable. Voltage supervision is then handed off to the precise low voltage reset (PRES) circuit. When the voltage is high enough for PRES to release, the IMO starts. PRES - Precise Low Voltage Reset This circuit monitors the outputs of the analog and digital internal regulators after power up. The regulator outputs are compared to a precise reference voltage. The response to a PRES trip is identical to an IPOR reset. In normal operating mode, the program cannot disable the digital PRES circuit. The analog regulator can be disabled, which also disables the analog portion of the PRES. The PRES circuit is disabled automatically during sleep and hibernate modes, with one exception: During sleep mode the regulators are periodically activated (buzzed) to provide supervisory Page 33 of 119
6.3 Reset
CY8C32 has multiple internal and external reset sources available. The reset sources are: Power source monitoring - The analog and digital power voltages, VDDA, VDDD, VCCA, and VCCD are monitored in several different modes during power up, active mode, and sleep mode (buzzing). If any of the voltages goes outside predetermined ranges then a reset is generated. The monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. External - The device can be reset from an external source by pulling the reset pin (XRES) low. The XRES pin includes an internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must all have voltage applied before the part comes out of reset. Watchdog timer - A watchdog timer monitors the execution of instructions by the processor. If the watchdog timer is not reset
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PSoC(R) 3: CY8C32 Family Data Sheet
services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when VDDA and VDDD go outside a voltage range. For AHVI, VDDA is compared to a fixed trip level. For ALVI and DLVI, VDDA and VDDD are compared to trip levels that are programmable, as listed in Table 6-5. ALVI and DLVI can also be configured to generate a device reset instead of an interrupt. Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt Supply DLVI Normal Voltage Range VDDD 1.71 V - 5.5 V VDDA 1.71 V - 5.5 V VDDA 1.71 V - 5.5 V Available Trip Accuracy Settings 1.70 V - 5.45 V in 250 mV increments 1.70 V - 5.45 V in 250 mV increments 5.75 V 2%
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and digital I/O capability. All I/Os have a large number of drive modes, which are set at POR. PSoC also provides up to four individual I/O voltage domains through the VDDIO pins. There are two types of I/O pins on every device; those with USB provide a third type. Both GPIO and Special I/O (SIO) provide similar digital functionality. The primary differences are their analog capability and drive strength. Devices that include USB also provide two USBIO pins that support specific USB functionality as well as limited GPIO capability. All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition, all I/O pins can generate an interrupt. The flexible and advanced capabilities of the PSoC I/O, combined with any signal to any pin routability, greatly simplify circuit design and board layout. All GPIO pins can be used for analog input, CapSense, and LCD segment drive, while SIO pins are used for voltages in excess of VDDA and for programmable output voltages. Features supported by both GPIO and SIO: User programmable port reset state Separate I/O supplies and voltages for up to four groups of I/O Digital peripherals use DSI to connect the pins Input or output or both for CPU and DMA Eight drive modes Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive interrupts are supported through the DSI Dedicated port interrupt vector for each port Slew rate controlled digital output drive mode Access port control and configuration registers on either port basis or pin basis Separate port read (PS) and write (DR) data registers to avoid read modify write errors Special functionality on a pin by pin basis Additional features only provided on the GPIO pins: LCD segment drive on LCD equipped devices CapSense Analog input and output capability Continuous 100 A clamp current capability Standard drive strength down to 1.7 V Additional features only provided on SIO pins: Higher drive strength than GPIO Hot swap capability (5 V tolerance at any operating VDD) Programmable and regulated high input and output drive levels down to 1.2 V No analog input, CapSense, or LCD capability Over voltage tolerance up to 5.5 V SIO can act as a general purpose analog comparator USBIO features: Full speed USB 2.0 compliant I/O Highest drive strength for general purpose use Input, output, or both for CPU and DMA Input, output, or both for digital peripherals Digital output (CMOS) drive mode Each pin can be an interrupt source configured as rising edge, falling edge, or both edges Page 34 of 119
ALVI
2%
AHVI
2%
The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wake up sequence. The interrupt is then recognized and may be serviced. 6.3.1.2 Other Reset Sources XRES - External Reset PSoC 3 has either a single GPIO pin that is configured as an external reset or a dedicated XRES pin. Either the dedicated XRES pin or the GPIO pin, if configured, holds the part in reset while held active (low). The response to an XRES is the same as to an IPOR reset. The external reset is active low. It includes an internal pull-up resistor. XRES is active during sleep and hibernate modes. SRES - Software Reset A reset can be commanded under program control by setting a bit in the software reset register. This is done either directly by the program or indirectly by DMA access. The response to a SRES is the same as after an IPOR reset. Another register bit exists to disable this function. WRES - Watchdog Timer Reset The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified amount of time, then a reset is generated. Note IPOR disables the watchdog function. The program must enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be cleared again except by an IPOR power-on reset event.
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Figure 6-8. GPIO Block Diagram
Digital Input Path
PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Input Buffer Disable Interrupt Logic
Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Drive Logic Slew Cntl
0 1
Vddio Vddio In Vddio
PIN
OE
Analog
1
0 1 0 1
Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable PRT[x]AMUX Analog Mux Enable
Switches
LCD
PRT[x]LCD_COM_SEG PRT[x]LCD_EN LCD Bias Bus 5 Display Data Logic & MUX
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Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Input Buffer Disable Interrupt Logic Buffer Thresholds Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Drive Logic Slew Cntl
0 1
Driver Vhigh
In
PIN
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
USB Receiver Circuitry PRT[x]DBL_SYNC_IN USBIO_CR1[0,1] Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Interrupt Logic Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
PRT[x]SYNC_OUT USBIO_CR1[7] USB SIE Control for USB Mode USBIO_CR1[4,5] Digital System Output PRT[x]BYP USBIO_CR1[2] USBIO_CR1[3] USBIO_CR1[6]
0 1
D+ pin only USB or I/O
Vddd Vddd Vddd Vddd
In
Drive Logic
5k
1.5 k
PIN
D+ 1.5 k D+D- 5 k Open Drain
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PSoC(R) 3: CY8C32 Family Data Sheet
6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts a simplified pin view based on each of the eight drive modes. Table 6-6 shows the I/O pin's drive state based on the port data register value or digital array signal if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. Figure 6-11. Drive Mode
Vddio Vddio
DR PS
Pin
DR PS
Pin
DR PS
Pin
DR PS
Pin
0.
High Impedance Analog
1. High Impedance Digital
Vddio
2. Resistive Pull-Up
Vddio
3. Resistive Pull-Down
Vddio
DR PS
Pin
DR PS
Pin
DR PS
Pin
DR PS
Pin
4. Open Drain , Drives Low
5. Open Drain , Drives High
6. Strong Drive
7. Resistive Pull-Up and Pull-Down
Table 6-6. Drive Modes Diagram 0 1 2 3 4 5 6 7 Drive Mode High impedence analog High Impedance digital Resistive pull-up[13] Resistive pull-down[13] Open drain, drives low Open drain, drive high Strong drive Resistive pull-up and pull-down[13] PRTxDM2 0 0 0 0 1 1 1 1 PRTxDM1 0 0 1 1 0 0 1 1 PRTxDM0 0 1 0 1 0 1 0 1 PRTxDR = 1 High Z High Z Res High (5K) Strong High High Z Strong High Strong High Res High (5K) PRTxDR = 0 High Z High Z Strong Low Res Low (5K) Strong Low High Z Strong Low Res Low (5K)
Note 13. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
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PSoC(R) 3: CY8C32 Family Data Sheet
High Impedance Analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O's digital input buffer due to a floating voltage. This state is recommended for pins that are floating or that support an analog voltage. High impedance analog pins do not provide digital input functionality. To achieve the lowest chip current in sleep modes, all I/Os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the PSoC device or by external circuitry. High Impedance Digital The input buffer is enabled for digital signal input. This is the standard high impedance (HiZ) state recommended for digital inputs. Resistive pull-up or resistive pull-down Resistive pull-up or pull-down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common application for these modes. Resistive pull-up and pull-down are not available with SIO in regulated output mode. Open Drain, Drives High and Open Drain, Drives Low Open drain modes provide high impedance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. A common application for these modes is driving the I2C bus signal lines. Strong Drive Provides a strong CMOS output drive in either high or low state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal circumstances. This mode is often used to drive digital output signals or external FETs. Resistive pull-up and pull-down Similar to the resistive pull-up and resistive pull-down modes except the pin is always in series with a resistor. The high data state is pull-up while the low data state is pull-down. This mode is most often used when other signals that may cause shorts can drive the bus. Resistive pull-up and pull-down are not available with SIO in regulated output mode. 6.4.2 Pin Registers Registers to configure and interact with pins come in two forms that may be used interchangeably. All I/O registers are available in the standard port form, where each bit of the register corresponds to one of the port pins. This register form is efficient for quickly reconfiguring multiple port pins at the same time. I/O registers are also available in pin form, which combines the eight most commonly used port register bits into a single register for each pin. This enables very fast configuration changes to individual pins with a single register write.
6.4.3 Bidirectional Mode High-speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode such as strong drive (set using PRTxDM[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. The bidirectional capability is useful for processor busses and communications interfaces such as the SPI Slave MISO pin that requires dynamic hardware control of the output buffer. The auxiliary control bus routes up to 16 UDB or digital peripheral generated output enable signals to one or more pins. 6.4.4 Slew Rate Limited Mode GPIO and SIO pins have fast and slow output slew rate options for strong and open drain drive modes, not resistive drive modes. Because it results in reduced EMI, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz and 33 MHz. The slew rate is individually configurable for each pin, and is set by the PRTxSLW registers. 6.4.5 Pin Interrupts All GPIO and SIO pins are able to generate interrupts to the system. All eight pins in each port interface to their own Port Interrupt Control Unit (PICU) and associated interrupt vector. Each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. Depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to "1" and an interrupt request is sent to the interrupt controller. Each PICU has its own interrupt vector in the interrupt controller and the pin status register providing easy determination of the interrupt source down to the pin level. Port pin interrupts remain active in all sleep modes allowing the PSoC device to wake from an externally generated interrupt. While level sensitive interrupts are not directly supported; Universal Digital Blocks (UDB) provide this functionality to the system when needed. 6.4.6 Input Buffer Mode GPIO and SIO input buffers can be configured at the port level for the default CMOS input thresholds or the optional LVTTL input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 I/O Power Supplies Up to four I/O pin power supplies are provided depending on the device and package. Each I/O supply must be less than or equal to the voltage on the chip's analog (VDDA) pin. This feature allows users to provide different I/O voltage levels for different pins on the device. Refer to the specific device package pinout to determine VDDIO capability for a given port and pin. The SIO port pins support an additional regulated high output capability, as described in Adjustable Output Level.
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PSoC(R) 3: CY8C32 Family Data Sheet
6.4.8 Analog Connections These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. Each GPIO may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as ADC or comparators. In addition, one select pin provides direct connection to the high current DAC. 6.4.9 CapSense This section applies only to GPIO pins. All GPIO pins may be used to create CapSense buttons and sliders. See the "CapSense" section on page 57 for more information. 6.4.10 LCD Segment Drive This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the "LCD Direct Drive" section on page 57 for details. 6.4.11 Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO's respective VDDIO. SIO pins are individually configurable to output either the standard VDDIO level or the regulated output, which is based on an internally generated reference. Typically the voltage DAC (VDAC) is used to generate the reference (see Figure 6-12). The "DAC" section on page 58 has more details on VDAC use and reference routing to the SIO pins. Resistive pull-up and pull-down drive modes are not available with SIO in regulated output mode. 6.4.12 Adjustable Input Level This section applies only to SIO pins. SIO pins by default support the standard CMOS and LVTTL input levels but also support a differential mode with programmable levels. SIO pins are grouped into pairs. Each pair shares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from VDDIO. The reference sets the pins voltage threshold for a high logic level (see Figure 6-12). Available input thresholds are: 0.5 x Vddio 0.4 x Vddio 0.5 x VREF VREF Typically the voltage DAC (VDAC) generates the VREF reference. The "DAC" section on page 58 has more details on VDAC use and reference routing to the SIO pins.
Figure 6-12. SIO Reference for Input and Output
Input Path
Digital Input
Vinref
SIO_Ref
Reference Generator
PIN
Voutref Output Path Driver Vhigh
Digital Output
Drive Logic
6.4.13 SIO as Comparator This section applies only to SIO pins. The adjustable input level feature of the SIOs as explained in the Adjustable Input Level section can be used to construct a comparator. The threshold for the comparator is provided by the SIO's reference generator. The reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. Note that a pair of SIO pins share the same threshold. The digital input path in Figure 6-9 on page 36 illustrates this functionality. In the figure, `Reference level' is the analog signal routed through the analog global. The hysteresis feature can also be enabled for the input buffer of the SIO, which increases noise immunity for the comparator. 6.4.14 Hot Swap This section applies only to SIO pins. SIO pins support `hot swap' capability to plug into an application without loading the signals that are connected to the SIO pins even when no power is applied to the PSoC device. This allows the unpowered PSoC to maintain a high impedance load to the external device while also preventing the PSoC from being powered through a GPIO pin's protection diode.
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PSoC(R) 3: CY8C32 Family Data Sheet
6.4.15 Over Voltage Tolerance All I/O pins provide an over voltage tolerance feature at any operating VDD. There are no current limitations for the SIO pins as they present a high impedance load to the external circuit where VDDIO < VIN < 5.5 V. The GPIO pins must be limited to 100 A using a current limiting resistor. GPIO pins clamp the pin voltage to approximately one diode above the VDDIO supply where VDDIO < VIN < VDDA. In case of a GPIO pin configured for analog input/output, the analog voltage on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. A common application for this feature is connection to a bus such as I2C where different devices are running from different supply voltages. In the I2C case, the PSoC chip is configured into the Open Drain, Drives Low mode for the SIO pin. This allows an external pull-up to pull the I2C bus voltage above the PSoC pin supply. For example, the PSoC chip could operate at 1.8 V, and an external device could run from 5 V. Note that the SIO pin's VIH and VIL levels are determined by the associated VDDIO supply pin. The I/O pin must be configured into a high impedance drive mode, open drain low drive mode, or pull-down drive mode, for over voltage tolerance to work properly. Absolute maximum ratings for the device must be observed for all I/O pins. 6.4.16 Reset Configuration While reset is active all I/Os are reset to and held in the High Impedance Analog state. After reset is released, the state can be reprogrammed on a port-by-port basis to pull-down or pull-up. To ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. The stored reset data is automatically transferred to the port reset configuration registers at reset release. 6.4.17 Low-Power Functionality In all low-power modes the I/O pins retain their state until the part is awakened and changed or reset. To awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low-power modes. 6.4.18 Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in Pinouts on page 5. The special features are: Digital 4- to 25- MHz crystal oscillator 32.768-kHz crystal oscillator Wake from sleep on I2C address match. Any pin can be used for I2C if wake from sleep is not required. JTAG interface pins SWD interface pins SWV interface pins External reset
Analog High current IDAC output External reference inputs 6.4.19 JTAG Boundary Scan The device supports standard JTAG boundary scan chains on all I/O pins for board level test.
7. Digital Subsystem
The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and IP security. The features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. You do not need to interact directly with the programmable digital system at the hardware and register level. PSoC Creator provides a high level schematic capture graphical interface to automatically place and route resources similar to PLDs. The main components of the digital programmable system are: Universal Digital Blocks (UDB) - These form the core functionality of the digital programmable system. UDBs are a collection of uncommitted logic (PLD) and structural logic (Datapath) optimized to create all common embedded peripherals and customized functionality that are application or design specific. Universal Digital Block Array - UDB blocks are arrayed within a matrix of programmable interconnect. The UDB array structure is homogeneous and allows for flexible mapping of digital functions onto the array. The array supports extensive and flexible routing interconnects between UDBs and the Digital System Interconnect. Digital System Interconnect (DSI) - Digital signals from Universal Digital Blocks (UDBs), fixed function peripherals, I/O pins, interrupts, DMA, and other system core signals are attached to the Digital System Interconnect to implement full featured device connectivity. The DSI allows any digital function to any pin or other feature routability when used with the Universal Digital Block Array.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 7-1. CY8C32 Digital Programmable Architecture
Digital Core System and Fixed Function Peripherals IO Port IO Port
7.1.2 Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C32 family. The exact amount of hardware resources (routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. ADC Delta-sigma DACs Current Voltage PWM Comparators 7.1.3 Example System Function Components The following is a sample of the system function components available in PSoC Creator for the CY8C32 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. CapSense LCD Drive LCD Control 7.1.4 Designing with PSoC Creator 7.1.4.1 More Than a Typical IDE A successful design tool allows for the rapid development and deployment of both simple and complex designs. It reduces or eliminates any learning curve. It makes the integration of a new design into the production stream straightforward. PSoC Creator is that design tool. PSoC Creator is a full featured Integrated Development Environment (IDE) for hardware and software design. It is optimized specifically for PSoC devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. This unique combination of tools makes PSoC Creator the most flexible embedded design platform available. Graphical design entry simplifies the task of configuring a particular part. You can select the required functionality from an extensive catalog of components and place it in your design. All components are parameterized and have an editor dialog that allows you to tailor functionality to your needs. PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the application complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. At any stage of development you are free to change the hardware configuration and even the target processor. To retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. You also have the ability to change the C compiler and evaluate an alternative. Components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. Switching compilers is as easy as editing the from the project options and rebuilding the application with no errors from the generated APIs or boot code. Page 41 of 119
DSI Routing Interface
UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB
UDB Array
UDB UDB UDB UDB
IO Port
DSI Routing Interface IO Port
Digital Core System and Fixed Function Peripherals
7.1 Example Peripherals
The flexibility of the CY8C32 family's Universal Digital Blocks (UDBs) and Analog Blocks allow the user to create a wide range of components (peripherals). The most common peripherals were built and characterized by Cypress and are shown in the PSoC Creator component catalog, however, users may also create their own custom components using PSoC Creator. Using PSoC Creator, users may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. The number of components available through PSoC Creator is too numerous to list in the datasheet, and the list is always growing. An example of a component available for use in CY8C32 family, but, not explicitly called out in this datasheet is the UART component. 7.1.1 Example Digital Components The following is a sample of the digital components available in PSoC Creator for the CY8C32 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. Communications I2C UART SPI Functions EMIF PWMs Timers Counters Logic NOT OR XOR AND
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UDB Array
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Figure 7-2. PSoC Creator Framework
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7.1.4.2 Component Catalog Figure 7-3. Component Catalog
7.1.4.4 Software Development Figure 7-4. Code Editor
Anchoring the tool is a modern, highly customizable user interface. It includes project management and integrated editors for C and assembler source code, as well the design entry tools. Project build control leverages compiler technology from top commercial vendors such as ARM(R) Limited, KeilTM, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for ARM, with no restrictions on code size or end product distribution, are included with the tool distribution. Upgrading to more optimizing compilers is a snap with support for the professional Keil C51 product and ARM RealViewTM compiler. 7.1.4.5 Nonintrusive Debugging Figure 7-5. PSoC Creator Debugger
The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device. It is populated with an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and PWMs, plus analog components such as ADC and DAC, and communication protocols, such as I2C, and USB. See Example Peripherals on page 41 for more details about available peripherals. All content is fully characterized and carefully documented in datasheets with code examples, AC/DC specifications, and user code ready APIs. 7.1.4.3 Design Reuse The symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation.
With JTAG (4-wire) and SWD (2-wire) debug connectivity available on all devices, the PSoC Creator debugger offers full control over the target device with minimum intrusion. Breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows--register, locals, watch, call stack, memory and peripherals--make for an unparalleled level of visibility into the system. Document Number: 001-56955 Rev. *J Page 43 of 119
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity.
also contains input/output FIFOs, which are the primary parallel data interface between the CPU/DMA system and the UDB. Status and Control Module - The primary role of this block is to provide a way for CPU firmware to interact and synchronize with UDB operation. Clock and Reset Module - This block provides the UDB clocks and reset selection and control. 7.2.1 PLD Module The primary purpose of the PLD blocks is to implement logic expressions, state machines, sequencers, lookup tables, and decoders. In the simplest use model, consider the PLD blocks as a standalone resource onto which general purpose RTL is synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD and datapath blocks, where the PLD implements only the random logic and state portion of the function while the datapath (ALU) implements the more structured elements. Figure 7-7. PLD 12C4 Structure
PT0 PT1 PT2 PT3 PT4 PT5 PT6 TC TC TC TC TC TC TC TC TC TC TC TC IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 SELIN (carry in) TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC AND Array PT7 T T T T
7.2 Universal Digital Block
The Universal Digital Block (UDB) represents an evolutionary step to the next generation of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digital blocks provides coarse programmability in which a few fixed functions with a small number of options are available. The new UDB architecture is the optimal balance between configuration granularity and efficient implementation. A cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. To achieve this, UDBs consist of a combination of uncommitted logic (PLD), structured logic (Datapath), and a flexible routing scheme to provide interconnect between these elements, I/O connections, and other peripherals. UDB functionality ranges from simple self contained functions that are implemented in one UDB, or even a portion of a UDB (unused resources are available for other functions), to more complex functions that require multiple UDBs. Examples of basic functions are timers, counters, CRC generators, PWMs, dead band generators, and communications functions, such as UARTs, SPI, and I2C. Also, the PLD blocks and connectivity provide full featured general purpose programmable logic within the limits of the available resources. Figure 7-6. UDB Block Diagram
PLD Chaining Clock and Reset Control PLD 12C4 (8 PTs) PLD 12C4 (8 PTs)
OUT0
MC0 MC1 MC2 MC3
T T T T
T T T T
T T T T
T T T T
T T T T
T T T T
T T T T
Status and Control
OUT1
Datapath
OUT2
Datapath Chaining
OUT3
SELOUT (carry out)
OR Array
Routing Channel
The main component blocks of the UDB are: PLD blocks - There are two small PLDs per UDB. These blocks take inputs from the routing array and form registered or combinational sum-of-products logic. PLDs are used to implement state machines, state bits, and combinational logic equations. PLD configuration is automatically generated from graphical primitives. Datapath Module - This 8-bit wide datapath contains structured logic to implement a dynamically configurable ALU, a variety of compare configurations and condition generation. This block
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12 inputs, which feed across eight product terms. Each product term (AND function) can be from 1 to 12 inputs wide, and in a given product term, the true (T) or complement (C) of each input can be selected. The product terms are summed (OR function) to create the PLD outputs. A sum can be from 1 to 8 product terms wide. The 'C' in 12C4 indicates that the width of the OR gate (in this case 8) is constant across all outputs (rather than variable as in a 22V10 device). This PLA like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. There are two 12C4 PLDs in each UDB.
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7.2.2 Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators and many others. Figure 7-8. Datapath Top Level
PHUB System Bus R/W Access to All Registers F1 FIFOs Datapath Control Control Store RAM 8 Word X 16 Bit Input from Programmable Routing Input Muxes 6 F0 A0 A1 D0 D1 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect Output Muxes 6 Output to Programmable Routing
D1 Data Registers D0
A1 Accumulators A0 PI Parallel Input/Output (To/From Programmable Routing) PO
To/From Previous Datapath
Chaining
To/From Next Datapath
ALU Shift Mask
7.2.2.1 Working Registers The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Table 7-1. Working Datapath Registers Name Function Description These are sources and sinks for the ALU and also sources for the compares. These are sources for the ALU and sources for the compares. These are the primary interface to the system bus. They can be a data source for the data registers and accumulators or they can capture data from the accumulators or ALU. Each FIFO is four bytes deep. A0 and A1 Accumulators
D0 and D1 Data Registers F0 and F1 FIFOs
7.2.2.2 Dynamic Datapath Configuration RAM Dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. This is implemented using the 8-word x 16-bit configuration RAM, which stores eight unique 16-bit wide configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the UDB routing matrix, most typically PLD logic, I/O pins, or from the outputs of this or other datapath blocks. ALU The ALU performs eight general purpose functions. They are: Increment Decrement Add Subtract Logical AND Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Page 45 of 119
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Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask 7.2.2.3 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are the primary datapath outputs, a selection of which can be driven out to the UDB routing matrix. Conditional computation can use the built in chaining to neighboring UDBs to operate on wider data widths without the need to use routing resources. 7.2.2.4 Variable MSB The most significant bit of an arithmetic and shift function can be programmatically specified. This supports variable width CRC and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.5 Built in CRC/PRS The datapath has built in support for single cycle Cyclic Redundancy Check (CRC) computation and Pseudo Random Sequence (PRS) generation of arbitrary width and arbitrary polynomial. CRC/PRS functions longer than 8 bits may be implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. 7.2.2.6 Input/Output FIFOs Each datapath contains two four-byte deep FIFOs, which can be independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA. Figure 7-9. Example FIFO Configurations
System Bus System Bus
7.2.2.7 Chaining The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithmetic, shift, CRC/PRS functions. 7.2.2.8 Time Multiplexing In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be selected as inputs in subsequent cycles. This provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.9 Datapath I/O There are six inputs and six outputs that connect the datapath to the routing matrix. Inputs from the routing provide the configuration for the datapath operation to perform in each cycle, and the serial data inputs. Inputs can be routed from other UDB blocks, other device peripherals, device I/O pins, and so on. The outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to other UDB blocks, device peripherals, interrupt and DMA controller, I/O pins, and so on. 7.2.3 Status and Control Module The primary purpose of this circuitry is to coordinate CPU firmware interaction with internal UDB operation. Figure 7-10. Status and Control Registers
System Bus
8-bit Status Register (Read Only)
8-bit Control Register (Write/Read)
Routing Channel
F0
F0
F1
The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. 7.2.3.1 Usage Examples As an example of control input, a bit in the control register can be allocated as a function enable bit. There are multiple ways to enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example is a case where a PLD or datapath block generated a condition, such as a "compare true" condition that is captured and latched by the status register and then read (and cleared) by CPU firmware.
D0/D1 A0/A1/ALU
A0/A1/ALU
A0/A1/ALU
D0 A0
D1 A1
F1
F0
F1
System Bus TX/RX
System Bus Dual Capture Dual Buffer
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7.2.3.2 Clock Generation Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component blocks and allows unused UDB resources to be used by other functions for maximum system efficiency.
7.3 UDB Array Description
Figure 7-11 shows an example of a 16 UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to UDBs, at horizontal/vertical intersection and at the DSI interface are highly permutable providing efficient automatic routing in PSoC Creator. Additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. Figure 7-11. Digital System Interface Structure
System Connections
An example of this is the 8-bit Timer in the upper left corner of the array. This function only requires one datapath in the UDB, and therefore the PLD resources may be allocated to another function. A function such as a Quadrature Decoder may require more PLD logic than one UDB can supply and in this case can utilize the unused PLD blocks in the 8-bit Timer UDB. Programmable resources in the UDB array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. Figure 7-12. Function Mapping Example in a Bank of UDBs
Sequencer 8-Bit Timer Quadrature Decoder UDB UDB 16-Bit PWM UDB 16-Bit PYRS UDB
HV A
HV B
HV A
HV B
UDB I2C Slave UDB
UDB 8-Bit SPI
UDB
UDB 8-Bit Timer Logic
12-Bit SPI UDB UDB UDB
HV B
HV A
HV B
HV A
HV B
HV A Logic
HV B
HV A
UDB
UDB
UDB
UDB
UDB
UDB
UDB 12-Bit PWM
UDB
HV A
HV B
HV A
HV B
UART
UDB
UDB
UDB
UDB
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array core. It provides general purpose programmable routing between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. Figure 7-13 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function peripheral that needs programmable routing is connected to this interface. Signals in this category include: Interrupt requests from all digital peripherals in the system. DMA requests from all digital peripherals in the system. Digital peripheral data signals that need flexible routing to I/Os. Digital peripheral data signals that need connections to UDBs. Connections to the interrupt and DMA controllers. Connection to I/O pins. Connection to analog system digital signals.
UDB
UDB
UDB
UDB
HV B
HV A
HV B
HV A
UDB
UDB
UDB
UDB
HV A
HV B
HV A
HV B
System Connections
7.3.1 UDB Array Programmable Resources Figure 7-12 shows an example of how functions are mapped into a bank of 16 UDBs. The primary programmable resources of the UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions.
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Figure 7-13. Digital System Interconnect
Tim ers C ounters I2C Interrupt C ontroller DMA C ontroller IO Port Pins G lobal C locks
conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Figure 7-15. I/O Pin Synchronization Routing
D igital System R outing I/F
UDB ARRAY
DO DI
D igital System R outing I/F
Figure 7-16. I/O Pin Output Connectivity
8 IO Data Output Connections from the UDB Array Digital System Interface
G lobal C locks
I/O Port Pins
EM IF
D el-Sig
D AC
C om parators
Interrupt and DMA routing is very flexible in the CY8C32 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure 7-14 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Figure 7-14. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX Fixed Function IRQs
DO PIN 0
DO PIN1
DO PIN2
DO PIN3
DO PIN4
DO PIN5
DO PIN6
DO PIN7
Port i
0 1 IRQs 2 Edge Detect DRQs DMA termout (IRQs) 0 1 Edge Detect 2 DMA Controller 3
Interrupt Controller
There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. The output enable signal is useful for creating tri-state bidirectional pins and buses. Figure 7-17. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from UDB Array Digital System Interface
UDB Array
Fixed Function DRQs
7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In
OE PIN 0 OE PIN1 OE PIN2 OE PIN3 OE PIN4 OE PIN5 OE PIN6 OE PIN7
Port i
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7.5 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are detailed in the "I/O System and Routing" section on page 34. USB includes the following features: Eight unidirectional data endpoints One bidirectional control endpoint 0 (EP0) Shared 512-byte buffer for the eight data endpoints Dedicated 8-byte buffer for EP0 Three memory modes Manual Memory Management with No DMA Access Manual Memory Management with Manual DMA Access Automatic Memory Management with Automatic DMA Access Internal 3.3 V regulator for transceiver Internal 48 MHz main oscillator mode that auto locks to USB bus clock, requiring no external crystal for USB (USB equipped parts only) Interrupts on bus and each endpoint event, with device wakeup USB Reset, Suspend, and Resume operations Bus powered and self powered modes Figure 7-18. USB
Arbiter System Bus 512 X 8 SRAM D+ SIE (Serial Interface Engine) Interrupts 48 MHz IMO USB I/O D- External 22 Resistors
to any device pin and any internal digital signal accessible through the DSI. Each of the four instances has a compare output, terminal count output (optional complementary compare output), and programmable interrupt request line. The Timer/Counter/PWMs are configurable as free running, one shot, or Enable input controlled. The peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. The peripheral supports full 16-bit capture. Timer/Counter/PWM features include: 16-bit Timer/Counter/PWM (down count only) Selectable clock source PWM comparator (configurable for LT, LTE, EQ, GTE, GT) Period reload on start, reset, and terminal count Interrupt on terminal count, compare true, or capture Dynamic counter reads Timer capture mode Count while enable signal is asserted mode Free run mode One Shot mode (stop at end of period) Complementary PWM outputs with deadband PWM output kill Figure 7-19. Timer/Counter/PWM
Clock Reset Enable Capture Kill IRQ TC / Compare! Compare
Timer / Counter / PWM 16-bit
7.7 I2C
The I2C peripheral provides a synchronous two wire interface designed to interface the PSoC device with a two wire I2C serial communication bus. The bus is compliant with Philips `The I2C Specification' version 2.1. Additional I2C interfaces can be instantiated using Universal Digital Blocks (UDBs) in PSoC Creator, as required. To eliminate the need for excessive CPU intervention and overhead, I2C specific support is provided for status detection and generation of framing bits. I2C operates as a slave, a master, or multimaster (Slave and Master). In slave mode, the unit always listens for a start condition to begin sending or receiving data. Master mode supplies the ability to generate the Start and Stop conditions and initiate transactions. Multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. If Master mode is enabled and Slave mode is not enabled, the block does not generate interrupts on externally generated Start conditions. I2C interfaces through the DSI routing and allows direct connections to any GPIO or SIO pins.
7.6 Timers, Counters, and PWMs
The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been included on this PSoC device family. Additional and more advanced functionality timers, counters, and PWMs can also be instantiated in Universal Digital Blocks (UDBs) as required. PSoC Creator allows you to choose the timer, counter, and PWM features that they require. The tool set utilizes the most optimal resources available. The Timer/Counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the DSI routing. DSI routing allows input and output connections
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I2C provides hardware address detect of a 7-bit address without CPU intervention. Additionally the device can wake from low-power modes on a 7-bit hardware address match. If wakeup functionality is required, I2C pin connections are limited to the two special sets of SIO pins. I C features include: Slave and Master, Transmitter, and Receiver operation Byte processing for low CPU overhead Interrupt or polling CPU interface Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs) 7 or 10-bit addressing (10-bit addressing requires firmware support)
2
SMBus operation (through firmware support - SMBus supported in hardware in UDBs) 7-bit hardware address compare Wake from low-power modes on address match Data transfers follow the format shown in Figure 7-20. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
Figure 7-20. I2C Complete Transfer Timing
SDA
SCL
START Condition
1-7
8
9
1-7
8
9
1-7
8
9
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP Condition
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8. Analog Subsystem
The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of the analog subsystem are outlined here to provide an overview of capabilities and architecture. Flexible, configurable analog routing architecture provided by analog globals, analog mux bus, and analog local buses.
High resolution delta-sigma ADC. One 8-bit DAC that provides either voltage or current output. Two comparators with optional connection to configurable LUT outputs. CapSense subsystem to enable capacitive touch sensing. Precision reference for generating an accurate analog voltage for internal analog blocks.
Figure 8-1. Analog Subsystem Block Diagram
A N A L O G R O U T I N G
DAC
Precision Reference
A N A L O G R O U T I N G
DelSig ADC
Comparators
CMP CMP
GPIO Port
GPIO Port
CapSense Subsystem
Analog Interface
Config & Status Registers
PHUB
CPU
DSI Array
Clock Distribution
Decimator
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to perform application specific functions. The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory.
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8.1 Analog Routing
The CY8C32 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output connections to the different analog blocks. For information on how to make pin selections for optimal analog routing, refer to the application note, AN58304 - PSoC(R) 3 and PSoC(R) 5 - Pin Selection for Analog Designs. 8.1.1 Features Flexible, configurable analog routing architecture 16 analog globals (AG) and two analog mux buses (AMUXBUS) to connect GPIOs and the analog blocks Each GPIO is connected to one analog global and one analog mux bus
Eight analog local buses (abus) to route signals between the different analog blocks Multiplexers and switches for input and output selection of the analog blocks 8.1.2 Functional Description Analog globals (AGs) and analog mux buses (AMUXBUS) provide analog connectivity between GPIOs and the various analog blocks. There are 16 AGs in the CY8C32 family. The analog routing architecture is divided into four quadrants as shown in Figure 8-2. Each quadrant has four analog globals (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is connected to the corresponding AG through an analog switch. The analog mux bus is a shared routing resource that connects to every GPIO through an analog switch. There are two AMUXBUS routes in CY8C32, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure 8-2.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 8-2. CY8C32 Analog Interconnect
Vdda Vssa Vcca Vssd
swinn
swinp
AMUXBUSL AGL[4] AGL[5] AGL[6] AGL[7]
AMUXBUSR AGR[4] AGR[5] AGR[6] AGR[7] 44
*
*
AMUXBUSL
AGL[4] AGL[5]
AGL[6] AGL[7]
ExVrefL ExVrefL1
ExVrefL2
GPIO P0[4] GPIO P0[5] GPIO P0[6] GPIO P0[7] GPIO P4[2] GPIO P4[3] GPIO P4[4] GPIO P4[5] GPIO P4[6] GPIO P4[7] Vccd Vssd
01 2 3 4 56 7 0123
3210 76543210
* *
i0
swout swin
in0 out0 + comp0
LPF
5
in1 out1 comp1 + swin
swout
cmp1_vref
cmp0_vref (1.024V) vref_cmp1 (0.256V) bg_vda_res_en Vdda Vdda/2
refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) cmp_muxvn[1:0]
COMPARATOR
90
bg_vda_swabusl0
cmp1_vref
refbufr_ cmp
refbufl_ cmp
cmp0_vref (1.024V)
cmp1_vref
AGR[7] AGR[6] AGR[5]
vssa
Vssa
AGR[4] AMUXBUSR
refsel[1:0]
out ref in refbufl
CAPSENSE
refbufr
out ref in
refbuf_vref1 (1.024V) refbuf_vref2 (1.2V)
refsel[1:0]
ABUSL0 ABUSL1 ABUSL2 ABUSL3 v0 DAC0 i0
ABUSR0 ABUSR1 ABUSR2 ABUSR3
Vddd
AGL[1] AGL[2] AGL[3]
Vddio2
AMUXBUSL AGL[0]
:
TS ADC
VBE Vss ref
LPF
AGL[3] AGL[2] AGL[1] AGL[0] AMUXBUSL
AGR[3] AGR[2] AGR[1] AGR[0] AMUXBUSR
Connection
Vboost
Switch Resistance Small ( ~870 Ohms ) Large ( ~200 Ohms)
Notes: * Denotes pins on all packages LCD signals are not shown.
Vssb
Vssd
XRES
Vbat
Ind
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Vddio1
GPIO P2[5] GPIO P2[6] GPIO P2[7] SIO P12[4] SIO P12[5] GPIO P6[4] GPIO P6[5] GPIO P6[6] GPIO P6[7]
GPIO P5[0] GPIO P5[1] GPIO P5[2] GPIO P5[3] GPIO P1[0] GPIO P1[1] GPIO P1[2] GPIO P1[3] GPIO P1[4] GPIO P1[5]
Mux Group Switch Group
*
*
*
*
*
*
*
*
13
Rev #51 2-April-2010
AMUXBUSR
AGR[3] AGR[2] AGR[1]
AGR[0]
GPIO P6[0] GPIO P6[1] GPIO P6[2] GPIO P6[3] GPIO P15[4] GPIO P15[5] GPIO P2[0] GPIO P2[1] GPIO P2[2] GPIO P2[3] * GPIO P2[4] *
VIDAC
36
vcmsel[1:0] en_resvpwra
vpwra vpwra/2 dsm0_vcm_vref1 (0.8V) dsm0_vcm_vref2 (0.7V) dsm0_qtz_vref2 (1.2V) dsm0_qtz_vref1 (1.024V) Vdda Vdda/4
en_resvda
vssa
+ DSM0 -
DSM
28
vcm refs qtz_ref vref_vss_ext
refmux[2:0]
ExVrefL
ExVrefR
AMUXBUSL
01 23456 7 0123
ANALOG ANALOG GLOBALS BUS
ANALOG ANALOG BUS GLOBALS
3210 76543210
AMUXBUSR
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*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Vddio0
Vddio3
GPIO P3[6] GPIO P3[7] SIO P12[0] SIO P12[1] GPIO P15[2] GPIO P15[3]
SIO P12[2] SIO P12[3] GPIO P4[0] GPIO P4[1] GPIO P0[0] GPIO P0[1] GPIO P0[2] GPIO P0[3]
*
ExVrefR
GPIO P3[5] GPIO P3[4] GPIO P3[3] GPIO P3[2] GPIO P3[1] GPIO P3[0] GPXT * P15[1] GPXT * P15[0]
* * * * * *
Vccd Vssd Vddd
* P15[7] * P15[6]
GPIO P5[7] GPIO P5[6] GPIO P5[5] GPIO P5[4] SIO P12[7] SIO P12[6] GPIO * P1[7] GPIO * P1[6]
USB IO USB IO
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PSoC(R) 3: CY8C32 Family Data Sheet
Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C32, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in Figure 8-2. Using the abus saves the analog globals and analog mux buses from being used for interconnecting the analog blocks. Multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. A multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure 8-2, multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals.
muxes is delivered to the delta-sigma modulator either directly or through the input buffer. The delta-sigma modulator performs the actual analog to digital conversion. The modulator over-samples the input and generates a serial data stream output. This high speed data stream is not useful for most applications without some type of post processing, and so is passed to the decimator through the Analog Interface block. The decimator converts the high speed serial data stream into parallel ADC results. The modulator/decimator frequency response is [(sin x)/x]4; a typical frequency response is shown in Figure 8-5. Figure 8-4. Delta-sigma ADC Block Diagram
Positive Input Mux (Analog Routing) Negative Input Mux Input Buffer
8.2 Delta-sigma ADC
The CY8C32 device contains one delta-sigma ADC. This ADC offers differential input, high resolution and excellent linearity, making it a good ADC choice for measurement applications. The converter can be configured to output 12-bit resolution at data rates of up to 192 ksps. At a fixed clock rate, resolution can be traded for faster data rates as shown in Table 8-1 and Figure 8-3. Table 8-1. Delta-sigma ADC Performance Bits 12 8 Maximum Sample Rate (sps) 192 k 384 k SINAD (dB) 66 43
frequency Response. dB
Delta Sigma Modulator
Decimator
12 to 20 Bit Result EOC
SOC
Figure 8-5. Delta-sigma ADC Frequency Response, Normalized to Output, Sample Rate = 48 kHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 1,000 10,000
Input Frequency, Hz
Figure 8-3. Delta-sigma ADC Sample Rates, Range = 1.024 V
1,000,000
100,000
100,000
1,000,000
Input frequency, Hz Sample rates, sps
10,000
1,000
Continuous M ulti-Sam ple
Resolution, bits
Resolution and sample rate are controlled by the Decimator. Data is pipelined in the decimator; the output is a function of the last four samples. When the input multiplexer is switched, the output data is not valid until after the fourth sample after the switch. 8.2.2 Operational Modes The ADC can be configured by the user to operate in one of four modes: Single Sample, Multi Sample, Continous, or Multi Sample (Turbo). All four modes are started by either a write to the start bit in a control register or an assertion of the Start of Conversion (SoC) signal. When the conversion is complete, a status bit is set and the output signal End of Conversion (EoC) asserts high and remains high until the value is read by either the DMA controller or the CPU.
100 7 8 9 10 11 12 13
8.2.1 Functional Description The ADC connects and configures three basic components, input buffer, delta-sigma modulator, and decimator. The basic block diagram is shown in Figure 8-4. The signal from the input
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PSoC(R) 3: CY8C32 Family Data Sheet
8.2.2.1 Single Sample In Single Sample mode, the ADC performs one sample conversion on a trigger. In this mode, the ADC stays in standby state waiting for the SoC signal to be asserted. When SoC is signaled the ADC performs four successive conversions. The first three conversions prime the decimator. The ADC result is valid and available after the fourth conversion, at which time the EoC signal is generated. To detect the end of conversion, the system may poll a control register for status or configure the external EoC signal to generate an interrupt or invoke a DMA request. When the transfer is done the ADC reenters the standby state where it stays until another SoC event. 8.2.2.2 Continuous Continuous sample mode is used to take multiple successive samples of a single input signal. Multiplexing multiple inputs should not be done with this mode. There is a latency of three conversion times before the first conversion result is available. This is the time required to prime the decimator. After the first result, successive conversions are available at the selected sample rate. 8.2.2.3 Multi Sample Multi sample mode is similar to continuous mode except that the ADC is reset between samples. This mode is useful when the input is switched between multiple signals. The decimator is re-primed between each sample so that previous samples do not affect the current conversion. Upon completion of a sample, the next sample is automatically initiated. The results can be transferred using either firmware polling, interrupt, or DMA. More information on output formats is provided in the Technical Reference Manual.
8.2.3 Start of Conversion Input The SoC signal is used to start an ADC conversion. A digital clock or UDB output can be used to drive this input. It can be used when the sampling period must be longer than the ADC conversion time or when the ADC must be synchronized to other hardware. This signal is optional and does not need to be connected if ADC is running in a continuous mode. 8.2.4 End of Conversion Output The EoC signal goes high at the end of each ADC conversion. This signal may be used to trigger either an interrupt or DMA request.
8.3 Comparators
The CY8C32 family of devices contains two comparators in a device. Comparators have these features: Input offset factory trimmed to less than 5 mV Rail-to-rail common mode input range (VSSA to VDDA) Speed and power can be traded off by using one of three modes: fast, slow, or ultra low-power Comparator outputs can be routed to lookup tables to perform simple logic functions and then can also be routed to digital blocks The positive input of the comparators may be optionally passed through a low pass filter. Two filters are provided Comparator inputs can be connections to GPIO or DAC output 8.3.1 Input and Output Interface The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB Digital System Interface.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 8-6. Analog Comparator
From Analog Routing
+ comp0 _
ANAIF
+
comp1
_
From Analog Routing
4
4
4
4
4
4
4
4
LUT0
LUT1
LUT2
LUT3
UDBs
8.3.2 LUT The CY8C32 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of any LUT is routed to the digital system interface of the UDB array. From the digital system interface of the UDB array, these signals can be connected to UDBs, DMA controller, I/O, or the interrupt controller. The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated control word is shown in Table 8-2.
Table 8-2. LUT Function vs. Program Word and Inputs Control Word 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Output (A and B are LUT inputs) FALSE (`0') A AND B A AND (NOT B) A (NOT A) AND B B A XOR B A OR B A NOR B A XNOR B NOT B A OR (NOT B) NOT A (NOT A) OR B A NAND B TRUE (`1')
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PSoC(R) 3: CY8C32 Family Data Sheet
8.4 LCD Direct Drive
The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for external components. With a high multiplex ratio of up to 1/16, the CY8C32 family LCD driver system can drive a maximum of 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. PSoC Creator provides an LCD segment drive component. The component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and commons along with other options. The software configures the device to meet the required specifications. This is possible because of the programmability inherent to PSoC devices. Key features of the PSoC LCD segment system are: LCD panel direct driving Type A (standard) and Type B (low-power) waveform support Wide operating voltage range support (2 V to 5 V) for LCD panels Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels Internal bias voltage generation through internal resistor ladder Up to 62 total common and segment outputs Up to 1/16 multiplex for a maximum of 16 backplane/common outputs Up to 62 front plane/segment outputs for direct drive Drives up to 736 total segments (16 backplane x 46 front plane) Up to 64 levels of software controlled contrast Ability to move display data from memory buffer to LCD driver through DMA (without CPU intervention) Adjustable LCD refresh rate from 10 Hz to 150 Hz Ability to invert LCD display for negative image Three LCD driver drive modes, allowing power optimization Figure 8-7. LCD System
Global Clock LCD DAC
8.4.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC to directly drive the glass of the LCD. A register setting determines whether the pin is a common or segment. The pin's LCD driver then selects one of the six bias voltages to drive the I/O pin, as appropriate for the display data. 8.4.2 Display Data Flow The LCD segment driver system reads display data and generates the proper output voltages to the LCD glass to produce the desired image. Display data resides in a memory buffer in the system SRAM. Each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer into the Port Data Registers via DMA. 8.4.3 UDB and LCD Segment Control A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver through a set of dedicated LCD global routing channels. In addition to generating the global LCD control signals, the UDB also produces a DMA request to initiate the transfer of the next frame of LCD data. 8.4.4 LCD DAC The LCD DAC generates the contrast control and bias voltage for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias voltages are driven out to GPIO pins on a dedicated LCD bias bus, as required.
8.5 CapSense
The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific resource usage is detailed in each CapSense component in PSoC Creator. A capacitive sensing method using a delta-sigma modulator (CSD) is used. It provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code.
8.6 Temp Sensor
Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature sensor has its own auxiliary ADC.
UDB LCD Driver Block DMA Display RAM
PIN
PHUB
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PSoC(R) 3: CY8C32 Family Data Sheet
8.7 DAC
The CY8C32 parts contain a Digital to Analog Converter (DAC). The DAC is 8-bit and can be configured for either voltage or current output. The DAC supports CapSense, power supply regulation, and waveform generation. The DAC has the following features: Adjustable voltage or current output in 255 steps Programmable step size (range selection) Eight bits of calibration to correct 25 percent of gain error
Source and sink option for current output 8 Msps conversion rate for current output 1 Msps conversion rate for voltage output Monotonic in nature Data and strobe inputs can be provided by the CPU or DMA, or routed directly from the DSI Dedicated low-resistance output pin for high-current mode Figure 8-8. DAC Block Diagram
I
source Range 1x ,8x ,64x
Reference Source
Scaler
Vout R 3R I sink Range 1x ,8x ,64x
Iout
8.7.1 Current DAC The current DAC (IDAC) can be configured for the ranges 0 to 32 A, 0 to 256 A, and 0 to 2.048 mA. The IDAC can be configured to source or sink current.
8.7.2 Voltage DAC For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.024 V and 0 to 4.096 V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered).
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PSoC(R) 3: CY8C32 Family Data Sheet
9. Programming, Debug Interfaces, Resources
PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. Three interfaces are available: JTAG, SWD, and SWV. JTAG and SWD support all programming and debug features of the device. JTAG also supports standard JTAG scan chains for board level test and chaining multiple JTAG devices to a single JTAG connection. Complete Debug on Chip (DoC) functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE software provides fully integrated programming and debug support for PSoC devices. The low cost MiniProg3 programmer and debugger is designed to provide full programming and debug support of PSoC devices in conjunction with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV interfaces are fully compatible with industry standard third party tools. All DOC circuits are disabled by default and can only be enabled in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables DOC. Disabling DOC features, robust flash protection, and hiding custom analog and digital functionality inside the PSoC device provide a level of security not possible with multichip application solutions. Additionally, all device interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently disabling interfaces is not recommended in most applications because you cannot access the device later. Because all programming, debug, and test interfaces are disabled when Device Security is enabled, PSoCs with Device Security enabled may not be returned for failure analysis. Table 9-1. Debug Configurations Debug and Trace Configuration All debug and trace disabled JTAG SWD SWV SWD + SWV GPIO Pins Used 0 4 or 5 2 1 3
9.2 Serial Wire Debug Interface
The SWD interface is the preferred alternative to the JTAG interface. It requires only two pins instead of the four or five needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not provide access to scan chains or device chaining. The SWD clock frequency can be up to 1/3 of the CPU clock frequency. SWD uses two pins, either two of the JTAG pins (TMS and TCK) or the USBIO D+ and D- pins. The USBIO pins are useful for in system programming of USB solutions that would otherwise require a separate programming connector. One pin is used for the data clock and the other is used for data input and output. SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 s (key window) after reset, that pin pair (JTAG or USB) receives a predetermined sequence of 1s and 0s. SWD is used for debugging or programming the flash memory. The SWD interface can be enabled from the JTAG interface or disabled, allowing its pins to be used as GPIO. Unlike JTAG, the SWD interface can always be reacquired on any device during the key window. It can then be used to reenable the JTAG interface, if desired. When using SWD or JTAG pins as standard GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD or JTAG use.
9.3 Debug Features
Using the JTAG or SWD interface, the CY8C32 supports the following debug features: Halt and single-step the CPU View and change CPU and peripheral registers, and RAM addresses Eight program address breakpoints One memory access breakpoint--break on reading or writing any memory address and data value Break on a sequence of breakpoints (non recursive) Debugging at the full speed of the CPU Debug operations are possible while the device is reset, or in low-power modes Compatible with PSoC Creator and MiniProg3 programmer and debugger Standard JTAG programming and debugging interfaces make CY8C32 compatible with other popular third-party tools (for example, ARM / Keil)
9.4 Trace Features
The CY8C32 supports the following trace features when using JTAG or SWD: Trace the 8051 program counter (PC), accumulator register (ACC), and one SFR / 8051 core RAM register Trace depth up to 1000 instructions if all registers are traced, or 2000 instructions if only the PC is traced (on devices that include trace memory) Program address trigger to start tracing Trace windowing, that is, only trace when the PC is within a given range Two modes for handling trace buffer full: continuous (overwriting the oldest trace data) or break when trace buffer is full Page 59 of 119
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit transfers, whichever is least. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, allowing these pins to be used as General Purpose I/O (GPIO) instead. The JTAG interface is used for programming the flash memory, debugging, I/O scan chains, and JTAG device chaining.
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PSoC(R) 3: CY8C32 Family Data Sheet
9.5 Single Wire Viewer Interface
The SWV interface is closely associated with SWD but can also be used independently. SWV data is output on the JTAG interface's TDO pin. If using SWV, you must configure the device for SWD, not JTAG. SWV is not supported with the JTAG interface. SWV is ideal for application debug where it is helpful for the firmware to output data similar to 'printf' debugging on PCs. The SWV is ideal for data monitoring, because it requires only a single pin and can output data in standard UART format or Manchester encoded format. For example, it can be used to tune a PID control loop in which the output and graphing of the three error terms greatly simplifies coefficient tuning. The following features are supported in SWV: 32 virtual channels, each 32 bits long Simple, efficient packing and serializing protocol Supports standard UART format (N81)
single (or few) bit failures do not deassert the WOL output. The state of the NVL bits after wafer processing is truly random with no tendency toward 1 or 0. The WOL only locks the part after the correct 32-bit key (0x50536F43) is loaded into the NVL's volatile memory, programmed into the NVL's nonvolatile cells, and the part is reset. The output of the WOL is only sampled on reset and used to disable the access. This precaution prevents anyone from reading, erasing, or altering the contents of the internal memory. The user can write the key into the WOL to lock out external access only if no flash protection is set (see "Flash Security" on page 22). However, after setting the values in the WOL, a user still has access to the part until it is reset. Therefore, a user can write the key into the WOL, program the flash protection data, and then reset the part to lock it. If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via Serial Wire Debug (SWD) port to electrically identify protected parts. The user can write the key in WOL to lock out external access only if no flash protection is set. For more information on how to take full advantage of the security features in PSoC see the PSoC 3 TRM. Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products.
9.6 Programming Features
The JTAG and SWD interfaces provide full programming support. The entire device can be erased, programmed, and verified. You can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device erase. Individual flash blocks can be erased, programmed, and verified, if block security settings permit.
9.7 Device Security
PSoC 3 offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. The device security is activated by programming a 32-bit key (0x50536F43) to a Write Once Latch (WOL). The Write Once Latch is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper outputs a `1' if a super-majority (28 of 32) of its bits match a pre-determined pattern (0x50536F43); it outputs a `0' if this majority is not reached. When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of the latch. Matching all bits is intentionally not required, so that
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PSoC(R) 3: CY8C32 Family Data Sheet
10. Development Support
The CY8C32 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more.
Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers.
10.1 Documentation
A suite of documentation, supports the CY8C32 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component datasheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications.
10.2 Online
In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging interfaces, the CY8C32 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits.
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PSoC(R) 3: CY8C32 Family Data Sheet
11. Electrical Specifications
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the "Example Peripherals" section on page 41 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications Parameter TSTG Description Storage temperature Conditions Higher storage temperatures reduce NVL data retention time. Recommended storage temperature is +25 C 25 C. Extended duration storage temperatures above 85 C degrade reliability. Min -55 Typ 25 Max 100 Units C
VDDA VDDD VDDIO VCCA VCCD VSSA VGPIO[14] VSIO VIND VBAT Ivddio Vextref LU ESDHBM ESDCDM
Analog supply voltage relative to VSSA Digital supply voltage relative to VSSD I/O supply voltage relative to VSSD Direct analog core voltage input Direct digital core voltage input Analog ground voltage DC input voltage on GPIO DC input voltage on SIO Voltage at boost converter input Boost converter supply Current per VDDIO supply pin ADC external reference inputs Latch up current[15] Human body model Charge device model Electrostatic discharge voltage Electrostatic discharge voltage Pins P0[3], P3[2] Includes signals sourced by VDDA and routed internal to the pin Output disabled Output enabled
-0.5 -0.5 -0.5 -0.5 -0.5 VSSD -0.5 VSSD -0.5 VSSD -0.5 VSSD -0.5 0.5 VSSD -0.5 - - -140 750 500
- - - - - - - - - - - - - - - -
6 6 6 1.95 1.95 VSSD + 0.5 VDDIO + 0.5 7 6 5.5 5.5 100 2 140 - -
V V V V V V V V V V V mA V mA V V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above normal operating conditions the device may not operate to specification.
Notes 14. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO VDDA. 15. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
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PSoC(R) 3: CY8C32 Family Data Sheet
11.2 Device Level Specifications
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter VDDA VDDA VDDD VDDD VDDIO[17] VCCA VCCD IDD[18] Description Conditions Min 1.8 1.71 1.8 1.71 1.71 Analog core regulator disabled Digital core regulator disabled 1.71 1.71 Typ - 1.8 - 1.8 - 1.8 1.8 Max 5.5 1.89 VDDA[16] 1.89 VDDA[16] 1.89 1.89 Units V V V V V V V Analog supply voltage and input to Analog core regulator enabled analog core regulator Analog supply voltage, analog regulator bypassed Digital supply voltage relative to VSSD Digital supply voltage, digital regulator bypassed I/IO supply voltage relative to VSSIO Direct analog core voltage input (Analog regulator bypass) Direct digital core voltage input (Digital regulator bypass) Active Mode, VDD = 1.71 V-5.5 V Bus clock off. Execute from CPU instruction buffer. See "Flash Program Memory" on page 22. CPU at 3 MHz T = -40 C T = 25 C T = 85 C CPU at 6 MHz T = -40 C T = 25 C T = 85 C CPU at 12 MHz T = -40 C T = 25 C T = 85 C CPU at 24 MHz T = -40 C T = 25 C T = 85 C CPU at 48 MHz T = -40 C T = 25 C T = 85 C VDD = 3.3 V, T = 25 C, IMO and bus clock enabled, ILO = 1 kHz, CPU executing from flash and accessing SRAM, all other blocks off, all I/Os tied low. CPU at 3 MHz CPU at 6 MHz CPU at 12 MHz CPU at 24 MHz CPU at 48 MHz - - - - - - - - - - - - - - - - - - - - - 0.8 - - 1.2 - - 2.0 - - 3.5 - - 6.6 - 1.4 2.2 3.6 6.4 11.8 - - - - - - - - - - - - - - - - - - - - mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Analog core regulator disabled Digital core regulator enabled Digital core regulator disabled
Notes 16. The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies. 17. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO VDDA. 18. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets.
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-2. DC Specifications (continued) Parameter Description Sleep Mode
[20]
Conditions VDD = VDDIO = 4.5-5.5 V T = -40 C T = 25 C T = 85 C VDD = VDDIO = 2.7-3.6 V T = -40 C T = 25 C T = 85 C VDD = VDDIO = 1.71-1.95 V T = -40 C T = 25 C T = 85 C VDD = VDDIO = 2.7-3.6V T = 25 C
Min - - - - - - - - - -
Typ - - - - 1 - - - - -
Max - - - - - - - - - -
Units A A A A A A A A A A
CPU = OFF RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at 1 kHz)[21] WDT = OFF I2C Wake = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode Comparator = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF I2C Wake = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode I2C Wake = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode Hibernate Mode[20]
VDD = VDDIO = 2.7-3.6V
T= 25 C
-
-
-
A
VDD = VDDIO = 4.5-5.5 V Hibernate mode current All regulators and oscillators off. SRAM retention GPIO interrupts are active Boost = OFF SIO pins in single ended input, unregulated output mode
T = -40 C T = 25 C T = 85 C
- - - - - - - - -
- - - - 200 - - - -
- - - - - - - - -
nA nA nA nA nA nA nA nA nA
VDD = VDDIO = 2.7-3.6 V
T = -40 C T = 25 C T = 85 C
VDD = VDDIO = 1.71-1.95 V T = -40 C T = 25 C T = 85 C
Notes 19. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 20. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 21. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
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Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V, Temperature = 25 C
Figure 11-2. Active Mode Current vs Temperature and FCPU, VDD = 3.3 V
Figure 11-3. Active Mode Current vs VDD and Temperature, FCPU = 24 MHz
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-3. AC Specifications[22] Parameter FCPU FBUSCLK Svdd TIO_INIT TSTARTUP TSLEEP Description CPU frequency Bus frequency VDD ramp rate Time from VDDD/VDDA/VCCD/VCCA IPOR to I/O ports set to their reset states Time from VDDD/VDDA/VCCD/VCCA VCCA/VCCD = regulated from PRES to CPU executing code at VDDA/VDDD, no PLL used, IMO reset vector boot mode (12 MHz typ.) Wakeup from sleep mode - Application of non-LVD interrupt to beginning of execution of next CPU instruction Wakeup from hibernate mode - Application of external interrupt to beginning of execution of next CPU instruction Conditions 1.71 V VDDD 5.5 V 1.71 V VDDD 5.5 V Min DC DC - - Typ - - - - Max 50.01 50.01 1 10 Units MHz MHz V/ns s
-
-
66
s
-
-
15
s
THIBERNATE
-
-
100
s
Figure 11-4. FCPU vs. VDD
5.5 V
Vdd Voltage
3.3 V
Valid Operating Region
1.71 V
Valid Operating Region with SMP
0.5 V 0V DC 1 MHz 10 MHz 50 MHz
CPU Frequency
Note 22. Based on device characterization (Not production tested).
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11.3 Power Regulators
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description Input voltage VDDD Output voltage VCCD Regulator output capacitor Conditions Min 1.8 - - Typ - 1.80 1 Max 5.5 - - Units V V F
10%, X5R ceramic or better. The two VCCD pins must be shorted together, with as short a trace as possible, see Power System on page 29
Figure 11-5. Regulators VCC vs VDD
Figure 11-6. Digital Regulator PSRR vs Frequency and VDD
11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description Input voltage VDDA Output voltage VCCA Regulator output capacitor Conditions Min 1.8 - - Typ - 1.80 1 Max 5.5 - - Units V V F
10%, X5R ceramic or better
Figure 11-7. Analog Regulator PSRR vs Frequency and VDD
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PSoC(R) 3: CY8C32 Family Data Sheet
11.3.3 Inductive Boost Regulator. Table 11-6. Inductive Boost Regulator DC Specifications Unless otherwise specified, operating conditions are: VBAT = 2.4 V, VOUT = 2.7 V, IOUT = 40 mA, FSW = 400 kHz, LBOOST = 10 H, CBOOST = 22 F || 0.1 F Parameter VBAT IOUT Description Input voltage Includes startup Load current
[23, 24]
Conditions T=-35 C to +65 C Over entire temperature range VBAT = 1.6 - 3.6 V, VOUT = 3.6 - 5.0 V, external diode VBAT = 1.6 - 3.6 V, VOUT = 1.6 - 3.6 V, internal diode VBAT = 0.8 - 1.6 V, VOUT = 1.6 - 3.6 V, internal diode VBAT = 0.8 - 1.6 V, VOUT = 3.6 - 5.0 V, external diode VBAT = 0.5 - 0.8 V, VOUT = 1.6 - 3.6 V, internal diode
Min 0.5 0.68 - - - - - -
Typ - - - - - - - - 200 12
Max 3.6 3.6 50 75 30 20 15 700 - -
Units V V mA mA mA mA mA mA A A
ILPK IQ
Inductor peak current Quiescent current Boost active mode Boost standby mode, 32 khz external crystal oscillator, IOUT < 1 iA
- -
VOUT
Boost voltage range[25, 26] 1.8 V 1.9 V 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V 5.0 V External diode required 1.71 1.81 1.90 2.28 2.57 2.85 3.14 3.42 4.75 - - LBOOST = 10 H LBOOST = 22 H 70 82 1.80 1.90 2.00 2.40 2.70 3.00 3.30 3.60 5.00 - - 85 90 1.89 2.00 2.10 2.52 2.84 3.15 3.47 3.78 5.25 3.8 4.1 - - V V V V V V V V V % % % %
RegLOAD RegLINE
Load regulation Line regulation Efficiency
Notes 23. For output voltages above 3.6 V, an external diode is required. 24. Maximum output current applies for output voltages 4x input voltage. 25. Based on device characterization (Not production tested). 26. At boost frequency of 2 MHz, VOUT is limited to 2 x VBAT. At 400 kHz, VOUT is limited to 4 x VBAT.
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Table 11-7. Inductive Boost Regulator AC Specifications Unless otherwise specified, operating conditions are: VBAT = 2.4 V, VOUT = 2.7 V, IOUT = 40 mA, FSW = 400 kHz, LBOOST = 10 H, CBOOST = 22 F || 0.1 F. Parameter VRIPPLE FSW Description Ripple voltage (peak-to-peak) Switching frequency Conditions VOUT = 1.8 V, FSW = 400 kHz, IOUT = 10 mA Min - - Typ - 0.1, 0.4, or 2 Max 100 - Units mV MHz
Table 11-8. Recommended External Components for Boost Circuit Parameter LBOOST CBOOST IF VR Description Boost inductor Filter capacitor
[27]
Conditions
Min 4.7 10
Typ 10 22 - -
Max 47 47 - -
Units H F A V
External Schottky diode average forward current
External Schottky diode is required for VOUT > 3.6 V
1 20
Note 27. Based on device characterization (Not production tested).
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-8. Efficiency vs VOUT IOUT = 30 mA, VBAT ranges from 0.7 V to VOUT, LBOOST = 22 H
Figure 11-9. Efficiency vs VBAT IOUT = 30 mA, VOUT = 3.3 V, LBOOST = 22 H
Figure 11-10. Efficiency vs IOUT VBAT = 2.4 V, VOUT = 3.3 V
Figure 11-11. Efficiency vs IOUT VBAT ranges from 0.7 V to 3.3 V, LBOOST = 22 H
Figure 11-12. Efficiency vs Switching Frequency VOUT = 3.3 V, VBAT = 2.4 V, IOUT = 40 mA
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11.1 Inputs and Outputs
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.1.1 GPIO Table 11-9. GPIO DC Specifications Parameter Description VIH Input voltage high threshold VIL Input voltage low threshold VIH Input voltage high threshold VIH VIL VIL VOH VOL Rpullup Rpulldown IIL CIN VH Idiode Rglobal Rmux Input voltage high threshold Input voltage low threshold Input voltage low threshold Output voltage high Output voltage low Conditions CMOS Input, PRT[x]CTL = 0 CMOS Input, PRT[x]CTL = 0 LVTTL Input, PRT[x]CTL = 1, VDDIO < 2.7 V LVTTL Input, PRT[x]CTL = 1, VDDIO 2.7V LVTTL Input, PRT[x]CTL = 1, VDDIO < 2.7 V LVTTL Input, PRT[x]CTL = 1, VDDIO 2.7V IOH = 4 mA at 3.3 VDDIO IOH = 1 mA at 1.8 VDDIO IOL = 8 mA at 3.3 VDDIO IOL = 4 mA at 1.8 VDDIO Min 0.7 x VDDIO - 0.7 x VDDIO 2.0 - - VDDIO - 0.6 VDDIO - 0.5 - - 3.5 3.5 - - - - - - Typ - - - - - - - - - - 5.6 5.6 - - 40 - 320 220 Max - 0.3 x VDDIO - - 0.3 x VDDIO 0.8 - - 0.6 0.6 8.5 8.5 2 7 - 100 - - Units V V V V V V V V V V k k nA pF mV A
Pull-up resistor Pull-down resistor Input leakage current (absolute value)[29] 25 C, VDDIO = 3.0 V Input capacitance[29] Input voltage hysteresis (Schmitt-Trigger)[29] Current through protection diode to VDDIO and VSSIO Resistance pin to analog global bus 25 C, VDDIO = 3.0 V Resistance pin to analog mux bus 25 C, VDDIO = 3.0 V
Figure 11-13. GPIO Output High Voltage and Current
Figure 11-14. GPIO Output Low Voltage and Current
Note 28. Based on device characterization (Not production tested).
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-10. GPIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode[29] TfallF TriseS TfallS Fall time in Fast Strong Mode[29] Rise time in Slow Strong Mode[29] Fall time in Slow Strong Mode[29] GPIO output operating frequency 2.7 V < VDDIO < 5.5 V, fast strong drive mode 1.71 V < VDDIO < 2.7 V, fast strong drive mode 3.3 V < VDDIO < 5.5 V, slow strong drive mode 1.71 V < VDDIO < 3.3 V, slow strong drive mode GPIO input operating frequency 1.71 V < VDDIO < 5.5 V Conditions 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF Min - - - - - - - - Typ - - - - - - - - Max 12 12 60 60 33 20 7 3.5 Units ns ns ns ns MHz MHz MHz MHz
Fgpioout
Fgpioin
90/10% VDDIO
-
-
50
MHz
Figure 11-15. GPIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-16. GPIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load
Note 29. Based on device characterization (Not production tested).
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11.1.2 SIO Table 11-11. SIO DC Specifications Parameter Vinmax Vinref Description Maximum input voltage Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold VIH GPIO mode Differential input mode[30] Input voltage low threshold VIL GPIO mode Differential input mode[30] Output voltage high VOH Unregulated mode Regulated mode[30] Regulated VOL Rpullup Rpulldown IIL Pull-up resistor Pull-down resistor Input leakage current (absolute value)[31] VIH < Vddsio VIH > Vddsio CIN VH Idiode Input Capacitance[31] Input voltage hysteresis (Schmitt-Trigger)[31] Current through protection diode to VSSIO Single ended mode (GPIO mode) Differential mode 25 C, Vddsio = 3.0 V, VIH = 3.0 V 25 C, Vddsio = 0 V, VIH = 3.0 V - - - - - - - - - 40 35 - 14 10 7 - - 100 nA A pF mV mV A mode[30] Output voltage low VDDIO = 3.30 V, IOL = 25 mA VDDIO = 1.80 V, IOL = 4 mA - - 3.5 3.5 - - 5.6 5.6 0.8 0.4 8.5 8.5 V V k k IOH = 4 mA, VDDIO = 3.3 V IOH = 1 mA IOH = 0.1 mA VDDIO - 0.4 SIO_ref - 0.65 SIO_ref - 0.3 - - - - SIO_ref + 0.2 SIO_ref + 0.2 V V V CMOS input Hysteresis disabled - - - - 0.3 x VDDIO SIO_ref - 0.2 V V CMOS input Hysteresis disabled 0.7 x VDDIO SIO_ref + 0.2 - - - - V V VDDIO > 3.7 VDDIO < 3.7 1 1 - - VDDIO - 1 VDDIO - 0.5 V V Conditions All allowed values of Vddio and Vddd, see Section 11.2.1 Min - 0.5 Typ - - Max 5.5 0.52 x VDDIO Units V V
Notes 30. See Figure 6-9 on page 36 and Figure 6-12 on page 39 for more information on SIO reference 31. Based on device characterization (Not production tested).
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Figure 11-17. SIO Output HighVoltage and Current, Unregulated Mode
Figure 11-18. SIO Output Low Voltage and Current, Unregulated Mode
Figure 11-19. SIO Output High Voltage and Current, Regulated Mode
Table 11-12. SIO AC Specifications Parameter TriseF TfallF TriseS TfallS Description Rise time in Fast Strong Mode (90/10%)[32] Fall time in Fast Strong Mode (90/10%)[32] Rise time in Slow Strong Mode (90/10%)[32] Fall time in Slow Strong Mode (90/10%)[32] Conditions Cload = 25 pF, VDDIO = 3.3 V Cload = 25 pF, VDDIO = 3.3 V Cload = 25 pF, VDDIO = 3.0 V Cload = 25 pF, VDDIO = 3.0 V Min - - - - Typ - - - - Max 12 12 75 60 Units ns ns ns ns
Note 32. Based on device characterization (Not production tested).
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Table 11-12. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 2.7 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, fast strong drive mode 1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast strong drive mode 3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow strong drive mode 1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow strong drive mode 2.7 V < VDDIO < 5.5 V, Regulated output mode, fast strong drive mode 1.71 V < VDDIO < 2.7 V, Regulated output mode, fast strong drive mode 1.71 V < VDDIO < 5.5 V, Regulated output mode, slow strong drive mode SIO input operating frequency 1.71 V < VDDIO < 5.5 V Conditions 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF Output continuously switching into 25 pF Output continuously switching into 25 pF Output continuously switching into 25 pF Min - Typ - Max 33 Units MHz
-
-
16
MHz
-
-
5
MHz
Fsioout
-
-
4
MHz
-
-
20
MHz
-
-
10
MHz
-
-
2.5
MHz
Fsioin
90/10% VDDIO
-
-
50
MHz
Figure 11-20. SIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-21. SIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load
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PSoC(R) 3: CY8C32 Family Data Sheet
11.1.3 USBIO For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 63. Table 11-13. USBIO DC Specifications Parameter Rusbi Rusba Vohusb Volusb Vohgpio Volgpio Vdi Vcm Vse Rps2 Rext Zo CIN IIL Description USB D+ pull-up resistance USB D+ pull-up resistance Static output high Static output low Output voltage high, GPIO mode Output voltage low, GPIO mode Differential input sensitivity Differential input common mode range Single ended receiver threshold PS/2 pull-up resistance External USB series resistor USB driver output impedance Input leakage current (absolute value) Conditions With idle bus While receiving traffic 15 k 5% to Vss, internal pull-up enabled 15 k 5% to Vss, internal pull-up enabled IOH = 4 mA, VDDD 3 V IOL = 4 mA, VDDD 3 V |(D+)-(D-)| - - In PS/2 mode, with PS/2 pull-up enabled In series with each USB pin Including Rext 25 C, VDDD = 3.0 V Min 0.900 1.425 2.8 - 2.4 - - 0.8 0.8 3 21.78 (-1%) 28 - - Typ - - - - - - - - - - 22 - - - Max 1.575 3.090 3.6 0.3 - 0.3 0.2 2.5 2 7 22.22 (+1%) 44 20 2 Units k k V V V V V V V k pF nA
USB transceiver input capacitance -
Figure 11-22. USBIO Output High Voltage and Current, GPIO Mode
Figure 11-23. USBIO Output Low Voltage and Current, GPIO Mode
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Table 11-14. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Tjr2 Tdj1 Tdj2 Tfdeop Tfeopt Tfeopr Tfst Fgpio_out Tr_gpio Tf_gpio Conditions Min 12 - 0.25% -8 -5 -3.5 -4 -2 160 82 - - - - - - - Typ 12 - - - - - - - - - - - - - - Max 12 + 0.25% 8 5 3.5 4 5 175 - 14 20 6 12 40 12 40 Units MHz ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns
Receiver data jitter tolerance to next transition Receiver data jitter tolerance to pair transition Driver differential jitter to next transition Driver differential jitter to pair transition Source jitter for differential transition to SE0 transition Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition GPIO mode output operating 3 V VDDD 5.5 V frequency VDDD = 1.71 V Rise time, GPIO mode, 10%/90% VDDD > 3 V, 25 pF load VDDD VDDD = 1.71 V, 25 pF load Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load VDDD = 1.71 V, 25 pF load
Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode, VDDD = 3.3 V, 25 pF Load
Table 11-15. USB Driver AC Specifications Parameter Description Tr Transition rise time Tf Transition fall time TR Rise/fall time matching Vcrs Output signal crossover voltage Conditions Min - - 90% 1.3 Typ - - - - Max 20 20 111% 2 Units ns ns
VUSB_5, VUSB_3.3, see USB DC Specifications on page 93
V
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11.1.4 XRES Table 11-16. XRES DC Specifications Parameter Description VIH Input voltage high threshold VIL Input voltage low threshold Rpullup CIN VH Idiode Pull-up resistor Input capacitance[33] Input voltage hysteresis (Schmitt-Trigger)[33] Current through protection diode to VDDIO and VSSIO Conditions Min 0.7 x VDDIO - 3.5 - - - Typ - - 5.6 3 100 - Max - 0.3 x VDDIO 8.5 - - 100 Units V V k pF mV A
Table 11-17. XRES AC Specifications Parameter Description Reset pulse width TRESET Conditions Min 1 Typ - Max - Units s
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11.2 Analog Peripherals
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.2.1 Delta-sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 6.144 MHz Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 Unless otherwise specified, all charts and graphs show typical values Table 11-18. 12-bit Delta-sigma ADC DC Specifications Parameter Resolution Number of channels, single ended Number of channels, differential Monotonic Ge Gd Vos TCVos Gain error Gain drift Input offset voltage Temperature coefficient, input offset voltage Input voltage range, single ended[34] Input voltage range, differential unbuffered[34] Input voltage range, differential, buffered[34] Integral non linearity[34] Differential non linearity[34] Integral non linearity[34] Differential non linearity[34] ADC input resistance Differential pair is formed using a pair of GPIOs. Yes Buffered, buffer gain = 1, Range = 1.024 V, 25 C Buffered, buffer gain = 1, Range = 1.024 V Buffered, 16-bit mode, VDDA = 2.7 V, 25 C Buffer gain = 1, 16-bit, Range = 1.024 V Description Conditions Min 8 - - - - - - - VSSA VSSA VSSA Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered Input buffer used Input buffer bypassed, 12 bit, Range = 1.024 V - - - - 10 - 0.9 Typ - - - - - - - - - - - - - - - - 148[35] - Max 12 No. of GPIO No. of GPIO/2 - 0.2 50 0.1 55 VDDA VDDA VDDA - 1 1 1 1 1 - - 1.3 Units bits - - - % ppm/C mV V/C V V V LSB LSB LSB LSB M k V
INL12 DNL12 INL8 DNL8 Rin_Buff
Rin_ADC12 ADC input resistance Vextref
ADC external reference input voltage, see also internal reference in Voltage Pins P0[3], P3[2] Reference on page 81 Current Consumption IDD_12 Current consumption, 12 bit[34] 192 ksps, unbuffered IBUFF Buffer current consumption[34]
- -
- -
1.4 2.5
mA mA
Notes
34. Based on device characterization (Not production tested). 35. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-19. Delta-sigma ADC AC Specifications Parameter Startup time THD Total harmonic distortion[36] Buffer gain = 1, 16 bit, Range = 1.024 V Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered Description Conditions Min - - Typ - - Max 4 0.0032 Units Samples %
12-Bit Resolution Mode SR12 BW12 SINAD12int Sample rate, continuous, high power[36] Input bandwidth at max sample rate[36] Signal to noise ratio, 12-bit, internal reference[36] Sample rate, continuous, high power[36] Input bandwidth at max sample rate[36] Signal to noise ratio, 8-bit, internal reference[36] 4 - 66 - 44 - 192 - - ksps kHz dB
8-Bit Resolution Mode SR8 BW8 SINAD8int Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered Range = 1.024 V, unbuffered 8 - 43 - 88 - 384 - - ksps kHz dB
Table 11-20. Delta-sigma ADC Sample Rates, Range = 1.024 V Resolution, Bits 8 9 10 11 12 Continuous Min 8000 6400 5566 4741 4000 Max 384000 307200 267130 227555 192000 Multi-Sample Min 1911 1543 1348 1154 978 Max 91701 74024 64673 55351 46900
Figure 11-25. Delta-sigma ADC IDD vs sps, Range = 1.024 V, Continuous Sample Mode, Input Buffer Bypassed
Note 36. Based on device characterization (Not production tested).
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PSoC(R) 3: CY8C32 Family Data Sheet
11.2.2 Voltage Reference Table 11-21. Voltage Reference Specifications See also ADC external reference specifications in Section 11.2.1. Parameter VREF Description Precision reference voltage Conditions Initial trim Min 1.014 (-1%) Typ 1.024 Max 1.034 (+1%) Units V
11.2.3 Analog Globals Table 11-22. Analog Globals Specifications Parameter Rppag Description Resistance pin-to-pin through analog global[37] bus[37] Conditions VDDA = 3.0 V VDDA = 3.0 V Min - - Typ 939 721 Max 1461 1135 Units
Rppmuxbus Resistance pin-to-pin through analog mux 11.2.4 Comparator Table 11-23. Comparator DC Specifications Parameter VOS Input offset voltage in slow mode VOS VOS VHYST VICM Input offset voltage in fast mode[38] Input offset voltage in slow mode[38] Input offset voltage in ultra low-power mode Hysteresis Input common mode voltage Description Input offset voltage in fast mode
Conditions Factory trim, Vdda > 2.7 V, Vin 0.5 V Factory trim, Vin 0.5 V Custom trim Custom trim
Min - - - - -
Typ
Max 10 9
Units mV mV mV mV mV mV V V dB A A A
- - 12 10 - - - 50 - - 6
4 4 - 32 VDDA - 0.1 VDDA VDDA - 0.9 - 400 100 -
Hysteresis enable mode High current / fast mode Low current / slow mode Ultra low power mode
- VSSA VSSA VSSA - - - -
CMRR ICMP
Common mode rejection ratio High current mode/fast mode[39] Low current mode/slow mode[39] Ultra low-power mode[39]
Table 11-24. Comparator AC Specifications Parameter Tresp Description Response time, high current mode[39] mode[39] Response time, low current mode[39] Response time, ultra low-power Conditions 50 mV overdrive, measured pin-to-pin 50 mV overdrive, measured pin-to-pin 50 mV overdrive, measured pin-to-pin Min - - - Typ 75 155 55 Max 110 200 - Units ns ns s
Notes 37. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended 38. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. 39. Based on device characterization (Not production tested).
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PSoC(R) 3: CY8C32 Family Data Sheet
11.2.5 Current Digital-to-analog Converter (IDAC) See the IDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-25. IDAC DC Specifications Parameter Resolution IOUT Output current at code = 255 Range = 2.048 mA, code = 255, VDDA 2.7 V, Rload = 600 Range = 2.048 mA, High mode, code = 255, VDDA 2.7 V, Rload = 300 Range = 255 A, code = 255, Rload = 600 Range = 31.875 A, code = 255, Rload = 600 Monotonicity Ezs Eg Zero scale error Gain error Range = 2.048 mA, 25 C Range = 255 A, 25 C Range = 31.875 A, 25 C TC_Eg Temperature coefficient of gain error Integral nonlinearity Range = 2.048 mA Range = 255 A Range = 31.875 A INL Sink mode, range = 255 A, Codes 8 - 255, Rload = 2.4 k, Cload = 15 pF Source mode, range = 255 A, Codes 8 - 255, Rload = 2.4 k, Cload = 15 pF DNL Differential nonlinearity Sink mode, range = 255 A, Rload = 2.4 k, Cload = 15 pF Source mode, range = 255 A, Rload = 2.4 k, Cload = 15 pF Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current, Rload to Vdda or Rload to Vssa, Vdiff from Vdda Description Conditions Min - - - Typ - 2.048 2.048 Max 8 - - Units bits mA mA
- - - - - - - - - - -
255 31.875 - 0 - - - - - - 0.9
- - Yes 1 2.5 2.5 3.5 0.04 0.04 0.05 1
A A
LSB % % % % / C % / C % / C LSB
-
1.2
1.5
LSB
- - 1
0.3 0.3 -
1 1 -
LSB LSB V
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-25. IDAC DC Specifications (continued) Parameter IDD Description Operating current, code = 0 Conditions Slow mode, source mode, range = 31.875 A Slow mode, source mode, range = 255 A, Slow mode, source mode, range = 2.04 mA Slow mode, sink mode, range = 31.875 A Slow mode, sink mode, range = 255 A Slow mode, sink mode, range = 2.04 mA Fast mode, source mode, range = 31.875 A Fast mode, source mode, range = 255 A Fast mode, source mode, range = 2.04 mA Fast mode, sink mode, range = 31.875 A Fast mode, sink mode, range = 255 A Fast mode, sink mode, range = 2.04 mA Figure 11-26. IDAC INL vs Input Code, Range = 255 A, Source Mode Min - - - - - - - - - - - - Typ 44 33 33 36 33 33 310 305 305 310 300 300 Max 100 100 100 100 100 100 500 500 500 500 500 500 Units A A A A A A A A A A A A
Figure 11-27. IDAC INL vs Input Code, Range = 255 A, Sink Mode
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-28. IDAC DNL vs Input Code, Range = 255 A, Source Mode
Figure 11-29. IDAC DNL vs Input Code, Range = 255 A, Sink Mode
Figure 11-30. IDAC INL vs Temperature, Range = 255 A, Fast Mode
Figure 11-31. IDAC DNL vs Temperature, Range = 255 A, Fast Mode
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Figure 11-32. IDAC Full Scale Error vs Temperature, Range = 255 A, Source Mode
Figure 11-33. IDAC Full Scale Error vs Temperature, Range = 255 A, Sink Mode
Figure 11-34. IDAC Operating Current vs Temperature, Range = 255 A, Code = 0, Source Mode
Figure 11-35. IDAC Operating Current vs Temperature, Range = 255 A, Code = 0, Sink Mode
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-26. IDAC AC Specifications Parameter FDAC TSETTLE Description Update rate Settling time to 0.5 LSB Range = 31.875 A or 255 A, full scale transition, fast mode, 600 15-pF load Conditions Min - - Typ - - Max 8 125 Units Msps ns
Figure 11-36. IDAC Step Response, Codes 0x40 - 0xC0, 255 A Mode, Source Mode, Fast Mode, Vdda = 5 V
Figure 11-37. IDAC Glitch Response, Codes 0x7F - 0x80, 255 A Mode, Source Mode, Fast Mode, Vdda = 5 V
Figure 11-38. IDAC PSRR vs Frequency
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PSoC(R) 3: CY8C32 Family Data Sheet
11.2.6 Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-27. VDAC DC Specifications Parameter Resolution INL1 DNL1 Rout VOUT Integral nonlinearity Differential nonlinearity Output resistance Output voltage range, code = 255 Monotonicity VOS Eg TC_Eg IDD Zero scale error Gain error 1 V scale 4 V scale Temperature coefficient, gain error 1 V scale 4 V scale Operating current Slow mode Fast mode Figure 11-39. VDAC INL vs Input Code, 1 V Mode 1 V scale 1 V scale 1 V scale 4 V scale 1 V scale 4 V scale, Vdda = 5 V Description Conditions Min - - - - - - - - - - - - - - - Typ 8 2.1 0.3 4 16 1 4 - 0 - - - - - - Max - 2.5 1 - - - - Yes 0.9 2.5 2.5 0.03 0.03 100 500 Units bits LSB LSB k k V V - LSB % % %FSR / C %FSR / C A A
Figure 11-40. VDAC DNL vs Input Code, 1 V Mode
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-41. VDAC INL vs Temperature, 1 V Mode
Figure 11-42. VDAC DNL vs Temperature, 1 V Mode
Figure 11-43. VDAC Full Scale Error vs Temperature, 1 V Mode
Figure 11-44. VDAC Full Scale Error vs Temperature, 4 V Mode
Figure 11-45. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode
Figure 11-46. VDAC Operating Current vs Temperature, 1 V Mode, Fast Mode
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-28. VDAC AC Specifications t Parameter FDAC TsettleP Description Update rate 1 V scale 4 V scale Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF 75% 4 V scale, Cload = 15 pF TsettleN Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF 25% 4 V scale, Cload = 15 pF Figure 11-47. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, Fast Mode, Vdda = 5 V Conditions Min - - - - - - Typ - - 0.45 0.8 0.45 0.7 Max 1000 250 1 3.2 1 3 Units ksps ksps s s s s
Figure 11-48. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, Fast Mode, Vdda = 5 V
Figure 11-49. VDAC PSRR vs Frequency
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PSoC(R) 3: CY8C32 Family Data Sheet
11.2.7 Temperature Sensor Table 11-29. Temperature Sensor Specifications Parameter Description Temp sensor accuracy 11.2.8 LCD Direct Drive Table 11-30. LCD Direct Drive DC Specifications Parameter ICC Description LCD system operating current Conditions Device sleep mode with wakeup at 400-Hz rate to refresh LCDs, bus clock = 3 Mhz, Vddio = Vdda = 3 V, 4 commons, 16 segments, 1/4 duty cycle, 50 Hz frame rate, no glass connected Strong drive mode Min - Typ 38 Max - Units A Conditions Range: -40 C to +85 C Min - Typ 5 Max - Units C
ICC_SEG VBIAS
Current per segment driver
- 2 - - -
260 - 9.1 x VDDA 500 - -
- 5 - 5000 20 710
A V mV pF mV A
LCD bias range (VBIAS refers to the VDDA 3 V and VDDA VBIAS main output voltage(V0) of LCD DAC) LCD bias step size LCD capacitance per segment/common driver Long term segment offset VDDA 3 V and VDDA VBIAS Drivers may be combined
IOUT
Output drive current per segment driver)
Vddio = 5.5V, strong drive mode
355
Table 11-31. LCD Direct Drive AC Specifications Parameter Description LCD frame rate fLCD Conditions Min 10 Typ 50 Max 150 Units Hz
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11.3 Digital Peripherals
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.3.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component datasheet in PSoC Creator. Table 11-32. Timer DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 50 MHz Table 11-33. Timer AC Specifications Parameter Description Operating frequency Capture pulse width (Internal) Capture pulse width (external) Timer resolution Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) 11.3.2 Counter The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in UDBs; for more information, see the Counter component datasheet in PSoC Creator. Table 11-34. Counter DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 50 MHz Table 11-35. Counter AC Specifications Parameter Description Operating frequency Capture pulse Resolution Pulse width Pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) Conditions Min DC 21 21 21 42 21 42 21 42 Typ - - - - - - - - - Max 50.01 - - - - - - - - Units MHz ns ns ns ns ns ns ns ns Conditions 16-bit counter, at listed input clock frequency Min - - - - Typ - 15 60 260 Max - - - - Units A A A A Conditions Min DC 21 42 21 21 42 21 42 Typ - - - - - - - - Max 50.01 - - - - - - - Units MHz ns ns ns ns ns ns ns Conditions 16-bit timer, at listed input clock frequency Min - - - - Typ - 15 60 260 Max - - - - Units A A A A
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PSoC(R) 3: CY8C32 Family Data Sheet
11.3.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator.. Table 11-36. PWM DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 50 MHz Table 11-37. Pulse Width Modulation (PWM) AC Specifications Parameter Pulse width Pulse width (external) Kill pulse width Kill pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) 11.3.4 I2C Table 11-38. Fixed I2C DC Specifications Parameter Description Block current consumption Conditions Enabled, configured for 100 kbps Enabled, configured for 400 kbps Wake from sleep mode Table 11-39. Fixed I2C AC Specifications Parameter Bit rate Controller Area Network[40] Table 11-40. CAN DC Specifications Parameter Description Block current consumption IDD Table 11-41. CAN AC Specifications Parameter Bit rate
Note 40. Refer to ISO 11898 specification for details.
Conditions 16-bit PWM, at listed input clock frequency
Min - - - -
Typ - 15 60 260
Max - - - -
Units A A A A
Description Operating frequency
Conditions
Min DC 21 42 21 42 21 42 21 42
Typ - - - - - - - - -
Max 50.01 - - - - - - - -
Units MHz ns ns ns ns ns ns ns ns
Min - - -
Typ - - -
Max 250 260 30
Units A A A
Description
Conditions
Min -
Typ -
Max 1
Units Mbps
Conditions
Min -
Typ -
Max 200
Units A
Description
Conditions Minimum 8 MHz clock
Min -
Typ -
Max 1
Units Mbit
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PSoC(R) 3: CY8C32 Family Data Sheet
11.3.5 USB Table 11-42. USB DC Specifications Parameter VUSB_5 VUSB_3.3 VUSB_3 Description Device supply for USB operation Conditions USB configured, USB regulator enabled USB configured, USB regulator bypassed USB configured, USB regulator bypassed[41] Min 4.35 3.15 2.85 - - - Typ - - - 10 8 0.5 Max 5.25 3.6 3.6 - - - Units V V V mA mA mA
IUSB_Configured Device supply current in device active VDDD = 5 V, FCPU = 1.5 MHz mode, bus clock and IMO = 24 MHz V DDD = 3.3 V, FCPU = 1.5 MHz IUSB_Suspended Device supply current in device sleep VDDD = 5 V, connected to USB mode host, PICU configured to wake on USB resume signal VDDD = 5 V, disconnected from USB host VDDD = 3.3 V, connected to USB host, PICU configured to wake on USB resume signal VDDD = 3.3 V, disconnected from USB host 11.3.6 Universal Digital Blocks (UDBs)
- -
0.3 0.5
- -
mA mA
-
0.3
-
mA
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-43. UDB AC Specifications Parameter Datapath Performance FMAX_TIMER Maximum frequency of 16-bit timer in a UDB pair FMAX_ADDER Maximum frequency of 16-bit adder in a UDB pair FMAX_CRC Maximum frequency of 16-bit CRC/PRS in a UDB pair Maximum frequency of a two-pass PLD function in a UDB pair Propagation delay for clock in to data 25 C, Vddd 2.7 V out, see Figure 11-50. Propagation delay for clock in to data Worst-case placement, routing, out, see Figure 11-50. and pin selection - - - - - - 50.01 50.01 50.01 MHz MHz MHz Description Conditions Min Typ Max Units
PLD Performance FMAX_PLD - - 50.01 MHz
Clock to Output Performance tCLK_OUT tCLK_OUT - - 20 - 25 55 ns ns
Note 41. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 77.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-50. Clock to Output Performance
11.4 Memory
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.4.1 Flash Table 11-44. Flash DC Specifications Parameter Description Erase and program voltage Table 11-45. Flash AC Specifications Parameter Description Row write time (erase + program) TWRITE Row erase time TERASE Row program time Bulk erase time (16 KB to 64 KB) TBULK Sector erase time (8 KB to 16 KB) Total device program time, including JTAG or SWD, and other overhead Flash data retention time, retention period measured from last erase cycle Conditions Min - - - - - - 20 Typ 15 10 5 - - - - Max 20 13 7 35 15 5 - Units ms ms ms ms ms seconds years VDDD pin Conditions Min 1.71 Typ - Max 5.5 Units V
Average ambient temp. TA 55 C, 100 K erase/program cycles Average ambient temp. TA 85 C, 10 K erase/program cycles
10
-
-
11.4.2 EEPROM Table 11-46. EEPROM DC Specifications Parameter Description Erase and program voltage Conditions Min 1.71 Typ - Max 5.5 Units V
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PSoC(R) 3: CY8C32 Family Data Sheet
Table 11-47. EEPROM AC Specifications Parameter Description Conditions Single row erase/write cycle time TWRITE EEPROM data retention time, retention Average ambient temp, TA 25 C, period measured from last erase cycle 1M erase/program cycles Average ambient temp, TA 55 C, 100 K erase/program cycles Average ambient temp. TA 85 C, 10 K erase/program cycles 11.4.3 Nonvolatile Latches (NVL)) Table 11-48. NVL DC Specifications Parameter Description Erase and program voltage Table 11-49. NVL AC Specifications Parameter Description NVL endurance Conditions Programmed at 25 C Min 1K Typ - Max - Units program/ erase cycles program/ erase cycles years years VDDD pin Conditions Min 1.71 Typ - Max 5.5 Units V Min - 20 20 10 Typ 2 - - - Max 20 - - - Units ms years
Programmed at 0 C to 70 C
100
-
-
NVL data retention time
Programmed at 25 C Programmed at 0 C to 70 C
20 20
- -
- -
11.4.4 SRAM Table 11-50. SRAM DC Specifications Parameter VSRAM Description SRAM retention voltage Conditions Min 1.2 Typ - Max - Units V
Table 11-51. SRAM AC Specifications Parameter FSRAM Description SRAM operating frequency Conditions Min DC Typ - Max 50.01 Units MHz
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PSoC(R) 3: CY8C32 Family Data Sheet
11.4.5 External Memory Interface Figure 11-51. Asynchronous Read Cycle Timing
Tcel
EM_ CEn
Taddrv Taddrh
EM_ Addr
Address
Toel
EM_ OEn
EM_ WEn
Tdoesu Tdoeh
EM_ Data
Table 11-52. Asynchronous Read Cycle Specifications Parameter T Tcel Taddrv Taddrh Toel Tdoesu Tdoeh Description EMIF clock period[42] EM_CEn low time EM_CEn low to EM_Addr valid Address hold time after EM_Wen high EM_OEn low time Data to EM_OEn high setup time Data hold time after EM_OEn high
Data
Conditions Vdda 3.3 V
Min 30.3 2T - 5 - T 2T - 5 T + 15 3
Typ - - - - - - -
Max - 2T+ 5 5 - 2T + 5 - -
Units nS nS nS nS nS nS nS
Note 42. Limited by GPIO output frequency, see Table 11-10 on page 72.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-52. Asynchronous Write Cycle Timing
Taddrv Taddrh
EM_ Addr
Tcel
Address
EM_ CEn
Twel
EM_ WEn EM_ OEn
Tdweh Tdcev
EM_ Data
Data
Table 11-53. Asynchronous Write Cycle Specifications Parameter T Tcel Taddrv Taddrh Twel Tdcev Tdweh EMIF clock Description period[43] EM_CEn low time EM_CEn low to EM_Addr valid Address hold time after EM_WEn high EM_WEn low time EM_CEn low to data valid Data hold time after EM_WEn high Conditions Vdda 3.3 V Min 30.3 T-5 - T T-5 - T Typ - - - - - - - Max - T+5 5 - T+5 7 - Units nS nS nS nS nS nS nS
Note 43. Limited by GPIO output frequency, see Table 11-10 on page 72.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-53. Synchronous Read Cycle Timing
Tcp/2
EM_ Clock
Tceld Tcehd
EM_ CEn
Taddrv Taddriv
EM_ Addr
Toeld Toehd
Address
EM_ OEn
Tds
EM_ Data
Tadscld Tadschd
Data
EM_ ADSCn
Table 11-54. Synchronous Read Cycle Specifications Parameter T Tcp/2 Tceld Tcehd Taddrv Taddriv Toeld Toehd Tds Tadscld Tadschd EMIF clock Description period[44] EM_Clock pulse high EM_CEn low to EM_Clock high EM_Clock high to EM_CEn high EM_Addr valid to EM_Clock high EM_Clock high to EM_Addr invalid EM_OEn low to EM_Clock high EM_Clock high to EM_OEn high Data valid before EM_OEn high EM_ADSCn low to EM_Clock high EM_Clock high to EM_ADSCn high Conditions Vdda 3.3 V Min 30.3 T/2 5 T/2 - 5 5 T/2 - 5 5 T T + 15 5 T/2 - 5 Typ - - - - - - - - - - - Max - - - - - - - - - - - Units nS nS nS nS nS nS nS nS nS nS nS
Note 44. Limited by GPIO output frequency, see Table 11-10 on page 72.
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PSoC(R) 3: CY8C32 Family Data Sheet
Figure 11-54. Synchronous Write Cycle Timing
Tcp/2
EM_ Clock
Tceld Tcehd
EM_ CEn
Taddrv Taddriv
EM_ Addr
Tweld
Address
Twehd
EM_ WEn
Tds Tdh
EM_ Data
Tadscld
Data
Tadschd
EM_ ADSCn
Table 11-55. Synchronous Write Cycle Specifications Parameter T Tcp/2 Tceld Tcehd Taddrv Taddriv Tweld Twehd Tds Tdh Tadscld Tadschd EMIF clock Description Period[45] EM_Clock pulse high EM_CEn low to EM_Clock high EM_Clock high to EM_CEn high EM_Addr valid to EM_Clock high EM_Clock high to EM_Addr invalid EM_WEn low to EM_Clock high EM_Clock high to EM_WEn high Data valid before EM_Clock high Data invalid after EM_Clock high EM_ADSCn low to EM_Clock high EM_Clock high to EM_ADSCn high Conditions Vdda 3.3 V Min 30.3 T/2 5 T/2 - 5 5 T/2 - 5 5 T/2 - 5 5 T 5 T/2 - 5 Typ - - - - - - - - - - - - Max - - - - - - - - - - - - Units nS nS nS nS nS nS nS nS nS nS nS nS
Note 45. Limited by GPIO output frequency, see Table 11-10 on page 72.
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PSoC(R) 3: CY8C32 Family Data Sheet
11.5 PSoC System Resources
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.5.1 POR with Brown Out For brown out detect in regulated mode, VDDD and VDDA must be 2.0 V. Brown out detect is not available in externally regulated mode. Table 11-56. Precise Power-on Reset (PRES) with Brown Out DC Specifications Parameter PRESR PRESF Description Precise POR (PPOR) Rising trip voltage Falling trip voltage Factory trim 1.64 1.62 - - 1.68 1.66 V V Conditions Min Typ Max Units
Table 11-57. Power-on Reset (POR) with Brown Out AC Specifications Parameter Description VDDD/VDDA droop rate 11.5.2 Voltage Monitors Table 11-58. Voltage Monitors DC Specifications Parameter Description LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = 1000b LVI_A/D_SEL[3:0] = 1001b LVI_A/D_SEL[3:0] = 1010b LVI_A/D_SEL[3:0] = 1011b LVI_A/D_SEL[3:0] = 1100b LVI_A/D_SEL[3:0] = 1101b LVI_A/D_SEL[3:0] = 1110b LVI_A/D_SEL[3:0] = 1111b HVI Trip voltage Table 11-59. Voltage Monitors AC Specifications Parameter Description Response time Conditions Min - Typ - Max 1 Units s Conditions Min 1.68 1.89 2.14 2.38 2.62 2.87 3.11 3.35 3.59 3.84 4.08 4.32 4.56 4.83 5.05 5.30 5.57 Typ 1.73 1.95 2.20 2.45 2.71 2.95 3.21 3.46 3.70 3.95 4.20 4.45 4.70 4.98 5.21 5.47 5.75 Max 1.77 2.01 2.27 2.53 2.79 3.04 3.31 3.56 3.81 4.07 4.33 4.59 4.84 5.13 5.37 5.63 5.92 Units V V V V V V V V V V V V V V V V V Conditions Sleep mode Min - - Typ - 5 Max 0.5 - Units s V/sec PRES_TR Response time
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11.5.3 Interrupt Controller Table 11-60. Interrupt Controller AC Specifications Parameter Description Conditions Min - Typ - Max 25 Units Tcy CPU Delay from interrupt signal input to ISR Includes worse case completion of code execution from ISR code longest instruction DIV with 6 cycles 11.5.4 JTAG Interface Figure 11-55. JTAG Interface Timing
(1/f_TCK)
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Table 11-61. JTAG Interface AC Specifications[46] Parameter f_TCK T_TDI_setup T_TMS_setup T_TDI_hold T_TDO_valid T_TDO_hold Description TCK frequency TDI setup before TCK high TMS setup before TCK high TDI, TMS hold after TCK high TCK low to TDO valid TDO hold after TCK high T = 1/f_TCK max T = 1/f_TCK max T = 1/f_TCK max Conditions 3.3 V VDDD 5 V 1.71 V VDDD < 3.3 V Min - - (T/10) - 5 T/4 T/4 - T/4 Typ - - - - - - - Max 14[47] 7[47] - - - 2T/5 - Units MHz MHz ns
Notes 46. Based on device characterization (Not production tested). 47. f_TCK must also be no more than 1/3 CPU clock frequency.
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11.5.5 SWD Interface Figure 11-56. SWD Interface Timing
(1/f_SWDCK)
SWDCK
T_SWDI_setup T_SWDI_hold
SWDIO (PSoC 3 reading on SWDIO)
T_SWDO_valid T_SWDO_hold
SWDIO (PSoC 3 writing to SWDIO)
Table 11-62. SWD Interface AC Specifications[48] Parameter f_SWDCK Conditions 3.3 V VDDD 5 V 1.71 V VDDD < 3.3 V 1.71 V VDDD < 3.3 V, SWD over USBIO pins T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max T_SWDO_valid SWDCK high to SWDIO output T = 1/f_SWDCK max T_SWDO_hold SWDIO output hold after SWDCK low T = 1/f_SWDCK max Description SWDCLK frequency Min - - - T/4 T/4 - T/4 Typ - - - - - - - Max 14[49] 7[49] 5.5[49] - - 2T/5 - Units MHz MHz MHz
11.5.6 SWV Interface Table 11-63. SWV Interface AC Specifications[22] Parameter Description SWV mode SWV bit rate Conditions Min - Typ - Max 33 Units Mbit
11.6 Clocking
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.6.1 32 kHz External Crystal Table 11-64. 32 kHz External Crystal DC Specifications[22] Parameter ICC CL DL Description Operating current External crystal capacitance Drive level Conditions Low-power mode Min - - - Typ 0.25 6 - Max 1.0 - 1 Units A pF W
Table 11-65. 32 kHz External Crystal AC Specifications Parameter F TON Frequency Startup time High power mode Description Conditions Min - - Typ 32.768 1 Max - - Units kHz s
Notes 48. Based on device characterization (Not production tested). 49. f_SWDCK must also be no more than 1/3 CPU clock frequency.
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11.6.2 Internal Main Oscillator Table 11-66. IMO DC Specifications Parameter Description Supply current 24 MHz - USB mode 24 MHz - non USB mode 12 MHz 6 MHz 3 MHz Figure 11-57. IMO Current vs. Frequency With oscillator locking to USB bus - - - - - - - - - - 500 300 200 180 150 A A A A A Conditions Min Typ Max Units
Table 11-67. IMO AC Specifications Parameter Description IMO frequency stability (with factory trim) 24 MHz - Non USB mode FIMO 24 MHz - USB mode 12 MHz 6 MHz 3 MHz Startup time[50] Jitter (peak to peak)[50] Jp-p F = 24 MHz F = 3 MHz Jitter (long term)[50] Jperiod F = 24 MHz F = 3 MHz - - 0.9 12 - - ns ns - - 0.9 1.6 - - ns ns From enable (during normal system operation) or wakeup from low-power state With oscillator locking to USB bus -4 -0.25 -3 -2 -1 - - - - - - - 4 0.25 3 2 1 12 % % % % % s Conditions Min Typ Max Units
Note 50. Based on device characterization (Not production tested).
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Figure 11-58. IMO Frequency Variation vs. Temperature
Figure 11-59. IMO Frequency Variation vs. VCC
11.6.3 Internal Low-Speed Oscillator Table 11-68. ILO DC Specifications Parameter ICC Leakage current Table 11-69. ILO AC Specifications Parameter Description Startup time, all frequencies ILO frequencies (trimmed) 100 kHz FILO 1 kHz ILO frequencies (untrimmed) 100 kHz 1 kHz 30 0.3 100 1 300 3.5 kHz kHz 45 0.5 100 1 200 2 kHz kHz Conditions Turbo mode Min - Typ - Max 2 Units ms Description Operating current Conditions FOUT = 1 kHz FOUT = 33 kHz FOUT = 100 kHz Power down mode Min - - - - Typ 0.3 1.0 1.0 2.0 Max 1.7 2.6 2.6 15 Units A A A nA
Figure 11-60. ILO Frequency Variation vs. Temperature
Figure 11-61. ILO Frequency Variation vs. VDD
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11.6.4 External Crystal Oscillator Table 11-70. ECO AC Specifications Parameter F Description Crystal frequency range Conditions Min 4 Typ - Max 25 Units MHz
11.6.5 External Clock Reference Table 11-71. External Clock Reference AC Specifications[51] Parameter Description External frequency range Input duty cycle range Input edge rate 11.6.6 Phase-Locked Loop Table 11-72. PLL DC Specifications Parameter IDD Description PLL operating current Conditions In = 3 MHz, Out = 24 MHz Min - Typ 200 Max - Units A Measured at VDDIO/2 VIL to VIH Conditions Min 0 30 0.1 Typ - 50 - Max 33 70 - Units MHz % V/ns
Table 11-73. PLL AC Specifications Parameter Fpllin Fpllout PLL input Description frequency[52] Output of prescaler PLL intermediate frequency[53] PLL output frequency[52] Lock time at startup Jperiod-rms Jitter (rms)[51] Conditions Min 1 1 24 - - Typ - - - - - Max 48 3 50 250 250 Units MHz MHz MHz s ps
Notes 51. Based on device characterization (Not production tested). 52. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 53. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
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PSoC(R) 3: CY8C32 Family Data Sheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C32 device includes: a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C32 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C32 Family with Single Cycle 8051
MCU Core LCD Segment Drive CPU Speed (MHz) Analog SC/CT Analog Blocks Digital 16-bit Timer/PWM I/O[55]
EEPROM (KB)
Comparator
SRAM (KB)
Part Number
Package CAN 2.0b Total I/O FS USB USBIO
JTAG ID[56]
Flash (KB)
CapSense
UDBs[54]
Opamps
GPIO
62 38 25 25 62 38 25 25 62 38 25 25 62 38 25 25
ADC
DAC
DFB
16 KB Flash
CY8C3244AXI-153 CY8C3244LTI-130 CY8C3244LTI-123 CY8C3244PVI-155 CY8C3244AXI-146 CY8C3244LTI-168 CY8C3244LTI-152 CY8C3244PVI-165 CY8C3244AXI-143 CY8C3244LTI-127 CY8C3244LTI-135 CY8C3244PVI-133 CY8C3244AXI-159 CY8C3244LTI-151 CY8C3244LTI-161 CY8C3244PVI-126 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 - - - - - - - - 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 - - - - - - - - - - - - - - - - - - - - - - - - 70 46 29 29 72 48 31 31 70 46 29 29 72 48 31 31 8 8 4 4 8 8 4 4 8 8 4 4 8 8 4 4 0 0 0 0 2 2 2 2 0 0 0 0 2 2 2 2 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 0x1E099069 0x1E082069 0x1E07B069 0x1E09B069 0x1E092069 0x1E0A8069 0x1E098069 0x1E0A5069 0x1E08F069 0x1E07F069 0x1E087069 0x1E085069 0x1E09F069 0x1E097069 0x1E0A1069 0x1E07E069
32 KB Flash
CY8C3245AXI-158 CY8C3245LTI-163 CY8C3245LTI-139 CY8C3245PVI-134 CY8C3245AXI-166 CY8C3245LTI-124 CY8C3245LTI-144 CY8C3245PVI-167 CY8C3245AXI-148 CY8C3245LTI-142 50 50 50 50 50 50 50 50 50 50 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 4 4 1 1 1 1 1 1 1 1 1 1 - - - - - - - - 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - 20 20 20 20 20 20 20 20 20 20 4 4 4 4 4 4 4 4 4 4 - - - - - - - - - - - - - - - - 70 46 29 29 72 48 31 31 70 46 62 38 25 25 62 38 25 25 62 38 8 8 4 4 8 8 4 4 8 8 0 0 0 0 2 2 2 2 0 0 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 0x1E09E069 0x1E0A3069 0x1E08B069 0x1E086069 0x1E0A6069 0x1E07C069 0x1E090069 0x1E0A7069 0x1E094069 0x1E08E069
Notes 54. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 41 for more information on how UDBs can be used. 55. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 34 for details on the functionality of each of these types of I/O. 56. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
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SIO
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Table 12-1. CY8C32 Family with Single Cycle 8051 (continued)
MCU Core LCD Segment Drive CPU Speed (MHz) Analog SC/CT Analog Blocks Digital 16-bit Timer/PWM I/O[58]
EEPROM (KB)
Comparator
SRAM (KB)
Part Number
Package CAN 2.0b Total I/O FS USB USBIO
JTAG ID[59]
Flash (KB)
CapSense
UDBs[57]
Opamps
GPIO
25 25 62 38 25 25
ADC
DAC
DFB
CY8C3245LTI-164 CY8C3245PVI-157 CY8C3245AXI-154 CY8C3245LTI-129 CY8C3245LTI-160 CY8C3245PVI-150
50 50 50 50 50 50
32 32 32 32 32 32
4 4 4 4 4 4
1 1 1 1 1 1

12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig
1 1 1 1 1 1
2 2 2 2 2 2
0 0 0 0 0 0
0 0 0 0 0 0
- - - - - -

20 20 20 20 20 20
4 4 4 4 4 4
- -
- - - - - -
29 29 72 48 31 31
SIO
4 4 8 8 4 4
0 0 2 2 2 2
48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP
0x1E0A4069 0x1E09D069 0x1E09A069 0x1E081069 0x1E0A0069 0x1E096069
64 KB Flash
CY8C3246AXI-137 CY8C3246LTI-149 CY8C3246LTI-136 CY8C3246PVI-141 CY8C3246AXI-140 CY8C3246LTI-145 CY8C3246LTI-121 CY8C3246PVI-147 CY8C3246AXI-131 CY8C3246LTI-156 CY8C3246LTI-162 CY8C3246PVI-122 CY8C3246AXI-138 CY8C3246LTI-128 CY8C3246LTI-125 CY8C3246PVI-132 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 - - - - - - - - 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 12-bit Del-Sig 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 - - - - - - - - - - - - - - - - - - - - - - - - 70 46 29 29 72 48 31 31 70 46 29 29 72 48 31 31 62 38 25 25 62 38 25 25 62 38 25 25 62 38 25 25 8 8 4 4 8 8 4 4 8 8 4 4 8 8 4 4 0 0 0 0 2 2 2 2 0 0 0 0 2 2 2 2 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 100-pin TQFP 68-pin QFN 48-pin QFN 48-pin SSOP 0x1E089069 0x1E095069 0x1E088069 0x1E08D069 0x1E08C069 0x1E091069 0x1E079069 0x1E093069 0x1E083069 0x1E09C069 0x1E0A2069 0x1E07A069 0x1E08A069 0x1E080069 0x1E07D069 0x1E084069
Notes 57. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 41 for more information on how UDBs can be used. 58. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 34 for details on the functionality of each of these types of I/O. 59. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
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PSoC(R) 3: CY8C32 Family Data Sheet
12.1 Part Numbering Conventions
PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, ..., 9, A, B, ..., Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC 5 b: Family group within architecture 2: CY8C32 family 4: CY8C34 family 6: CY8C36 family 8: CY8C38 family c: Speed grade 4: 50 MHz 6: 67 MHz d: Flash capacity 4: 16 KB 5: 32 KB 6: 64 KB ef: Package code Two character alphanumeric AX: TQFP LT: QFN PV: SSOP g: Temperature range C: commercial I: industrial A: automotive xxx: Peripheral set Three character numeric No meaning is associated with these three characters.
Example
Cypress Prefix 3: PSoC 3 2: CY8C32 Family 4: 50 MHz 6: 64 KB PV: SSOP I: Industrial Architecture Family Group within Architecture Speed Grade Flash Capacity Package Code Temperature Range Peripheral Set
CY8C
3246PV
I
-
xxx
All devices in the PSoC 3 CY8C32 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other "end of life" requirements.
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13. Packaging
Table 13-1. Package Characteristics Parameter TA TJ Tja Tja Tja Tja Tjc Tjc Tjc Tjc Description Operating ambient temperature Operating junction temperature Package JA (48-pin SSOP) Package JA (48-pin QFN) Package JA (68-pin QFN) Package JA (100-pin TQFP) Package JC (48-pin SSOP) Package JC (48-pin QFN) Package JC (68-pin QFN) Package JC (100-pin TQFP) Conditions Min -40 -40 - - - - - - - - Typ 25.00 - 45.16 15.94 11.72 30.52 27.84 7.05 6.32 9.04 Max 85 100 - - - - - - - - Units C C C/Watt C/Watt C/Watt C/Watt C/Watt C/Watt C/Watt C/Watt
Table 13-2. Solder Reflow Peak Temperature Package 48-pin SSOP 48-pin QFN 68-pin QFN 100-pin TQFP Maximum Peak Temperature 260 C 260 C 260 C 260 C Maximum Time at Peak Temperature 30 seconds 30 seconds 30 seconds 30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package 48-pin SSOP 48-pin QFN 68-pin QFN 100-pin TQFP MSL MSL 3 MSL 3 MSL 3 MSL 3
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Figure 13-1. 48-pin (300 mil) SSOP Package Outline
.020
24 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620 0.630
0.088 0.092
0.095 0.110
SEATING PLANE GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.004
0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85061-*D
Figure 13-2. 48-pin QFN Package Outline
TOP VIEW SIDE VIEW BOTTOM VIEW
7.000.10
1.00 MAX. 0.05 MAX. 0.20 REF.
5.60.10 0.230.05 37 48 1
PIN 1 ID
48 1 PIN 1 DOT LASER MARK
37 36 36
7.000.10 5.60.10
SOLDERABLE EXPOSED PAD
25 24 0.500.10 13 12
5.55 REF
12 13 24
25
0.400.10
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE
PART # LT48D DESCRIPTION LEAD FREE
0.08
C
5.55 REF
001- 45616 *B
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Figure 13-3. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version)
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.9000.100 8.0000.100 0.200 REF 5.70.10 0.400 PITCH PIN1 ID R 0.20
6 8 1
PIN 1 DOT
5 2 5 1 5 1
5 2
6 8
1
8.0000.100
5.70.10
0.200.05
1 7 1 8 3 4
3 5
0.05 MAX
SEATING PLANE
0.4000.1005
3 3 4
6.40 REF
1 8
1 7
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
0.08
C
001-09618 *C
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.17g 4. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 13-4. 100-pin TQFP (14 x 14 x 1.4 mm) Package Outline
51-85048 *E
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6.40 REF
LASER MARK
SOLDERABLE EXPOSED PAD
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PSoC(R) 3: CY8C32 Family Data Sheet
14. Acronyms
Table 14-1. Acronyms Used in this Document Acronym abus ADC AG AHB analog local bus analog-to-digital converter analog global AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus arithmetic logic unit analog multiplexer bus application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode bandwidth Controller Area Network, a communications protocol common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO. direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame execution program status register electrostatic discharge embedded trace macrocell Description
Table 14-1. Acronyms Used in this Document (continued) Acronym FIR FPB FS GPIO HVI IC IDAC IDE I2C, IIR ILO IMO INL I/O IPOR IPSR IRQ ITM LCD LIN LR LUT LVD LVI LVTTL MAC MCU MISO NC NMI NRZ NVIC NVL opamp PAL PC PCB PGA or IIC Description finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC integrated development environment Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell liquid crystal display Local Interconnect Network, a communications protocol. link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier Page 112 of 119
ALU AMUXBUS API APSR ARM(R) ATM BW CAN CMRR CPU CRC DAC DFB DIO DMA DNL DNU DR DSI DWT ECC ECO EEPROM EMI EMIF EOC EOF EPSR ESD ETM
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Table 14-1. Acronyms Used in this Document (continued) Acronym PHUB PHY PICU PLA PLD PLL PMDD POR PRES PRS PS PSoC(R) PSRR PWM RAM RISC RMS RTC RTL RTR RX SAR SC/CT SCL SDA S/H SINAD SIO SOC peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration datasheet power-on reset precise power-on reset pseudo random sequence port read data register Programmable System-on-ChipTM power supply rejection ratio pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time I
2C
Table 14-1. Acronyms Used in this Document (continued) Acronym SOF SPI SR SRAM SRES SWD SWV TD THD TIA TRM TTL TX UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL start of frame Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier technical reference manual transistor-transistor logic transmit Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal Description
Description
serial clock
I2C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO. start of conversion
15. Reference Documents
PSoC(R) 3, PSoC(R) 5 Architecture TRM PSoC(R) 3 Registers TRM
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16. Document Conventions
16.1 Units of Measure
Table 16-1. Units of Measure Symbol C dB fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A decibels femtofarads hertz 1024 bytes kilobits per second kilohours kilohertz kilohms kilosamples per second least significant bit megabits per second megahertz megaohms megasamples per second microamperes Unit of Measure degrees Celsius
Table 16-1. Units of Measure (continued) Symbol F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V microfarads microhenrys microseconds microvolts microwatts milliamperes milliseconds millivolts nanoamperes nanoseconds nanovolts ohms picofarads parts per million picoseconds seconds samples per second square root of hertz volts Unit of Measure
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PSoC(R) 3: CY8C32 Family Data Sheet
17. Revision History
Description Title: PSoC(R) 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-56955 Orig. of Rev. ECN No. Submission Change Description of Change Date ** 2796903 11/04/09 MKEA New datasheet *A 2824546 12/09/09 MKEA Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC and DC specs); also added Shottky Diode specs. Changed current for sleep/hibernate mode to include SIO; Added footnote to analog global specs. Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3 (Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO AC specifications. Updated Gain error in IDAC and VDAC specifications. Updated description of VDDA spec in Table 11-1 and removed GPIO Clamp Current parameter. Updated number of UDBs on page 1. Moved FILO from ILO DC to AC table. Added PCB Layout and PCB Schematic diagrams. Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec table. Added note for Sleep and Hibernate modes and Active Mode specs in Table 11-2. Linked URL in Section 10.3 to PSoC Creator site. Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table. Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC ADC. Updated Boost Converter section. Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode) in Table 11-10. Updated VBAT condition and deleted Vstart parameter in Table 11-6. Added 'Bytes' column for Tables 4-1 to 4-5. *B 2873322 02/04/10 MKEA Changed maximum value of PPOR_TR to '1'. Updated VBIAS specification. Updated PCB Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt Vector table, Updated Sales links. Updated JTAG and SWD specifications. Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer in Table 11-2. Updated ILO AC and DC specifications. Added Resolution parameter in VDAC and IDAC tables. Updated IOUT typical and maximum values. Changed Temperature Sensor range to -40 C to +85 C. Removed Latchup specification from Table 11-1. Updated DAC details
Document Number: 001-56955 Rev. *J
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PSoC(R) 3: CY8C32 Family Data Sheet
Description Title: PSoC(R) 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-56955 *C 2903576 04/01/10 MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in AC Specifications table. Added Load regulation and Line regulation parameters to Inductive Boost Regulator DC Specifications table. Updated ICC parameter in LCD Direct Drive DC Specs table. In page 1, updated internal oscillator range under Prescision programmable clocking to start from 3 MHz. Updated IOUT parameter in LCD Direct Drive DC Specs table. Updated Table 6-2 and Table 6-3. Added bullets on CapSense in page 1; added CapSense column in Section 12 Rem oved some references to footnote [1]. Changed INC_Rn cycles from 3 to 2 (Table 4-1). Added footnote in PLL AC Specification table. Added PLL intermediate frequency row with footnote in PLL AC Specs table. Added UDBs subsection under 11.6 Digital Peripherals. Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9. Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1. Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for VDDA and VDDD pins. Updated boost converter section (6.2.2). Updated Tstartup values in Table 11-3. Removed IPOR rows from Table 11-53. Updated 6.3.1.1, Power Voltage Level Monitors. Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash. Updated IMO max frequency in Figure 6-1, Table 11-63, and Table 11-64. Updated VREF specs in Table 11-19. Updated IDAC uncompensated gain error in Table 11-23. Updated Delay from Interrupt signal input to ISR code execution from ISR code in Table-71. Removed other line in table. Added sentence to last paragraph of section 6.1.1.3. Updated Tresp, high and low-power modes, in Table 11-22. Updated f_TCK values in Table 11-58 and f_SWDCK values in Table 11-59. Updated SNR condition in Table 11-18. Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3. Added 1.71 V <= VDDD < 3.3 V, SWD over USBIO pins value to Table 11-59. Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-53 (changed title, values TBD), and Table 11-54 (changed PPOR_TR to PRES_TR). Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1. Changed IDD values on page 1, page 5, and Table 11-2. Changed resume time value in Section 6.2.1.3. Changed ESD HBM value in Table 11-1. Changed sample rate row in Table 11-18. Removed VDDA = 1.65 V rows and changed BWag value in Table 11-20. Changed Vioff values and changed CMRR value in Table 11-21. Changed INL max value in Table 11-25. Changed occurrences of "Block" to "Row" and deleted the "ECC not included" footnote in Table 11-41. Changed max response time value in Tables 11-54 and 11-56. Change the Startup time in Table 11-64. Added condition to intermediate frequency row in Table 11-70. Added row to Table 11-54. Added brown out note to Section 11.8.1.
Document Number: 001-56955 Rev. *J
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PSoC(R) 3: CY8C32 Family Data Sheet
Description Title: PSoC(R) 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-56955 *D 2938381 05/27/10 MKEA Replaced VDDIO with VDDD in USBIO diagram and specification tables, added text in USBIO section of Electrical Specifications. Added Table 13-2 (Package MSL) Modified Tstorag condition and changed max spec to 100 Added bullet (Pass) under ALU (section 7.2.2.2) Added figures for kHzECO and MHzECO in the External Oscillator section Updated Figure 6-1(Clocking Subsystem diagram) Removed CPUCLK_DIV in table 5-2, Deleted Clock Divider SFR subsection Updated PSoC Creator Framework image Updated SIO DC Specifications (VIH and VIL parameters) Updated bullets in Clocking System and Clocking Distribution sections Updated Figure 8-2 Updated Table 11-10 Updated PCB Layout and Schematic, updated as per MTRB review comments Updated Table 6-3 (power changed to current) In 32kHZ EC DC Specifications table, changed ICC Max to 0.25 In IMO DC Specifications table, updated Supply Current values Updated GPIO DC Specs table Modified to support a maximum 50MHz CPU speed *E 2958674 06/22/10 SHEA Minor ECN to post datasheet to external website *F 2989685 08/04/10 MKEA Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram Added to Table 6-6 a footnote and references to same. Added sentences to the resistive pull-up and pull-down description bullets. Added sentence to Section 6.4.11, Adjustable Output Level. Updated section 5.5 External Memory Interface Updated Table 11-73 JTAG Interface AC Specifications Updated Table 11-74 SWD Interface AC Specifications *G 3078568 11/04/10 MKEA Updated "Current Digital-to-analog Converter (IDAC)" on page 82 Updated "Voltage Digital to Analog Converter (VDAC)" on page 87 Updated Table 11-2, "DC Specifications," on page 63 *H 3107314 12/10/2010 MKEA Updated delta-sigma tables and graphs. Updated Flash AC specs Formatted table 11.2. Updated interrupt controller table Updated transimpedance amplifier section Updated SIO DC specs table Updated Voltage Monitors DC Specifications table Updated LCD Direct Drive DC specs table Updated ESDHBM value. Updated IDAC and VDAC sections Removed ESO parts from ordering information Changed USBIO pins from NC to DNU and removed redundant USBIO pin description notes Updated POR with brown out DC and AC specs Updated 32 kHz External Crystal DC Specifications Updated XRES IO specs Updated Inductive boost regulator section Delta sigma ADC spec updates Updated comparator section Removed buzz mode from Power Mode Transition diagram *I 3179219 02/22/2011 MKEA Updated conditions for flash data retention time. Updated 100-pin TQFP package spec. Updated EEPROM AC specifications.
Document Number: 001-56955 Rev. *J
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PSoC(R) 3: CY8C32 Family Data Sheet
Description Title: PSoC(R) 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-56955 *J 3200146 03/28/2011 MKEA Removed Preliminary status from the data sheet. Updated JTAG ID Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table Updated JTAG Interface AC Specifications and SWD Interface Specifications tables Updated USBIO DC specs Added 0.01 to max speed Updated Features on page 1 Added Section 5.5, Nonvolatile Latches Updated Flash AC specs Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables Add reference to application note AN58304 in section 8.1 Updated 100-pin TQFP package spec Added oscillator, I/O, VDAC, regulator graphs Updated JTAG/SWD timing diagrams Updated GPIO and SIO AC specs Updated POR with Brown Out AC spec table UpdatedIDAC graphs Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing diagrams Added full chip performance graphs Changed MHzECO range. Added "Solder Reflow Peak Temperature" table.
Document Number: 001-56955 Rev. *J
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PSoC(R) 3: CY8C32 Family Data Sheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers' representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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PSoC Solutions
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(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-56955 Rev. *J
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Revised March 30, 2011
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CapSense , PSoC 3, PSoC 5, and PSoC CreatorTM are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
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